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1. 发明申请

US20180261304A1 APPARATUS AND METHOD FOR MEASURING ROUND-TRIP TIME OF TEST SIGNAL USING PROGRAMMABLE LOGIC 审中-公开
公开(公告)号：US20180261304A1
公开(公告)日：2018-09-13
申请号：US15976907
申请日：2018-05-11
申请人： UNITEST INC.
发明人： Ho Sang YOU
IPC分类号： G11C29/56
CPC分类号： G11C29/56012 , G11C29/1201 , G11C29/12015 , G11C29/16 , G11C29/36 , G11C29/48 , G11C29/56004 , G11C2029/3602 , H03K19/177
摘要： An apparatus for measuring round-trip time of a test signal using a programmable logic device comprises a pattern generator generating a test signal and measuring a round-trip time of the test signal, a programmable logic device of which internal circuits are configured to transmit the test signal in a predetermined manner, and bidirectional buses connecting the pattern generator and the programmable logic device. The round-trip time of the test signal is measured by a time difference between a starting time at which the pattern generator outputs the test signal and an arrival time at which the test signal is fed back to the pattern generator.

2. 发明申请

US20180144812A1 WIRE ORDER TESTING METHOD AND ASSOCIATED APPARATUS 审中-公开
公开(公告)号：US20180144812A1
公开(公告)日：2018-05-24
申请号：US15795548
申请日：2017-10-27
申请人： MediaTek Singapore Pte. Ltd.
发明人： Chun-Xue YU
IPC分类号： G11C29/38 , G01R31/319
CPC分类号： G11C29/38 , G01R31/31912 , G11C29/022 , G11C29/10 , G11C29/1201 , G11C29/12015 , G11C29/36 , G11C29/56004 , G11C29/56012 , G11C2029/3602 , G11C2029/5602
摘要： A wire order testing method for testing pin connection relationships between a memory device and an electronic device is provided. The method includes the steps of: testing the memory device with at least one test pattern to obtain at least one first data; predicting at least one second data that is to be obtained from the testing of the memory device with the test pattern according to the mapping relationships between the test pattern and the pins of the memory device; determining the pin connection relationships between the memory device and the electronic device according to the first data and second data.

3. 发明授权

US09934873B2 Delayed equivalence identification 有权
公开(公告)号：US09934873B2
公开(公告)日：2018-04-03
申请号：US15662354
申请日：2017-07-28
申请人： International Business Machines Corporation
发明人： Raj Kumar Gajavelly , Ashutosh Misra , Pradeep Kumar Nalla , Rahul M. Rao
IPC分类号： G11C7/10 , G11C29/54 , G11C7/22
CPC分类号： G11C29/54 , G11C7/10 , G11C7/22 , G11C29/023 , G11C29/56012 , G11C2029/5606
摘要： A method includes configuring an integrated circuit comprising one or more registers to provide a free running clock in the integrated circuit, simulating N clock cycles in the circuit to provide performance results for one or more registers in the circuit, wherein N is a selected number of staging levels, selecting one of the one or more registers, comparing the performance results for the selected register to performance results for each of the remaining registers to provide one or more equivalent delay candidate registers, and verifying each of the one or more equivalent delay candidate registers to provide one or more confirmed equivalent delay registers. A corresponding computer program product and computer system are also disclosed.

4. 发明申请

US20170199242A1 Technique for Determining Performance Characteristics Of Electronic Devices And Systems 有权
公开(公告)号：US20170199242A1
公开(公告)日：2017-07-13
申请号：US15389398
申请日：2016-12-22
申请人： Rambus Inc.
发明人： Haw-Jyh Liaw , Xingchao Yuan , Mark A. Horowitz
IPC分类号： G01R31/317 , G11C29/02 , G01R23/16
CPC分类号： G01R31/31708 , G01R23/16 , G01R23/20 , G01R31/31717 , G11C29/02 , G11C29/022 , G11C29/025 , G11C29/50012 , G11C29/56 , G11C29/56012 , G11C2029/5004 , H04B17/309
摘要： A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

5. 发明申请

US20170147019A1 CIRCUIT AND METHOD FOR GENERATING REFERENCE VOLTAGE BASED ON TEMPERATURE COEFFICIENT 有权
公开(公告)号：US20170147019A1
公开(公告)日：2017-05-25
申请号：US15265872
申请日：2016-09-15
申请人： Samsung Electronics Co., Ltd.
发明人： Jong-cheol Kim
IPC分类号： G05F1/46 , G11C11/4099 , G11C11/4074
CPC分类号： G05F1/468 , G11C5/147 , G11C7/04 , G11C7/14 , G11C11/4074 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/56012 , G11C2029/5602
摘要： An integrated circuit may include a reference voltage generating circuit for generating a reference voltage. The reference voltage generating circuit may include a digital operation circuit and a digital-to-analog converter. The digital operation circuit is configured to adjust a reference voltage to temperature code relationship using a coefficient that adjusts a relative relationship between the reference voltage and the temperature code, and separate code that adjusts an absolute relationship between the reference voltage and the temperature code, wherein the temperature code reflects a temperature at the integrated circuit. The digital-to-analog converter is configured to generate the reference voltage based on an output from the digital operation circuit

6. 发明申请

US20170140840A1 MEMORY DEVICE AND A MEMORY DEVICE TEST SYSTEM 有权
公开(公告)号：US20170140840A1
公开(公告)日：2017-05-18
申请号：US15224973
申请日：2016-08-01
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： WON-HWA SHIN
IPC分类号： G11C29/44 , G11C29/38 , G11C11/4076 , G11C29/36 , G11C29/52 , G11C11/408
CPC分类号： G11C29/44 , G11C7/1006 , G11C11/4096 , G11C29/1201 , G11C29/12015 , G11C29/14 , G11C29/18 , G11C29/26 , G11C29/34 , G11C29/36 , G11C29/38 , G11C29/46 , G11C29/52 , G11C29/56008 , G11C29/56012 , G11C2029/4402 , G11C2029/5602 , G11C2207/107
摘要： A memory device includes a controller, a multiplexer, a deserializer, a data modifier, a memory cell array and an error detector. The controller is configured to generate signals in response to an address signal and a command signal. The multiplexer is configured to output a clock signal as internal data signals when the test mode signal is activated. The deserializer is configured to deserialize N bit values included in the internal data signals to generate deserialized signals. The data modifier is configured to invert the deserialized signals to generate bit line signals in response to an inversion control signal and the data modifying signals. The memory cell array is configured to store the bit line signals to memory cells corresponding to the address signal. The error detector is configured to determine if an error exists in signals read from the memory cells and to output an error detecting signal.

7. 发明申请

US20170069358A1 MEMORY DEVICE AND METHOD OF OPERATION THEREOF 审中-公开
标题翻译：存储器件及其操作方法
公开(公告)号：US20170069358A1
公开(公告)日：2017-03-09
申请号：US15046090
申请日：2016-02-17
申请人： SK hynix Inc.
发明人： Tae-Sik YUN , Jae-Jin LEE
IPC分类号： G11C7/06 , G11C7/12
CPC分类号： G11C29/50012 , G11C29/56012 , G11C2207/2272
摘要： An operation method of a memory device may include writing first data to a plurality of memory cells corresponding to a plurality of word lines, enabling a sense amplifier corresponding to the memory cells and setting second data in the sense amplifier, the second data having the opposite phase of the first data, and sequentially enabling the plurality of word lines for a predetermined time while enabling the sense amplifier.
摘要翻译：存储器件的操作方法可以包括将第一数据写入与多个字线相对应的多个存储器单元，使得能够读出对应于存储器单元的读出放大器并设置读出放大器中的第二数据，第二数据具有相反的第一数据的相位，并且在启用读出放大器的同时，使多个字线顺序启用预定时间。

8. 发明授权

US09036437B2 Method and apparatus for testing memory utilizing a maximum width of a strobe signal and a data width of a data signal 有权
标题翻译：用于使用选通信号的最大宽度和数据信号的数据宽度来测试存储器的方法和装置
公开(公告)号：US09036437B2
公开(公告)日：2015-05-19
申请号：US14150783
申请日：2014-01-09
申请人： Wistron Corporation
发明人： Min-Hua Hsieh
IPC分类号： G11C29/00 , G11C29/04
CPC分类号： G11C29/56012 , G11C29/50012 , G11C2029/0407
摘要： A method and an apparatus for testing a memory are provided, and the method is adapted for an electronic apparatus to test the memory. In the method, a left edge and a right edge of a first waveform of a clock signal for testing the memory are scanned to obtain a maximum width between two cross points of the left edge and the right edge. A central reference voltage of a data signal outputted by the memory is obtained, and a data width between two cross points of the central reference voltage and a left edge and a right edge of a second waveform of the data signal is obtained. Whether a difference between the data width and the maximum width is greater than a threshold is determined; if the difference is greater than the threshold, the memory is determined to be damaged.
摘要翻译：提供了一种用于测试存储器的方法和装置，并且该方法适用于电子设备来测试存储器。在该方法中，扫描用于测试存储器的时钟信号的第一波形的左边缘和右边缘，以获得左边缘和右边缘的两个交叉点之间的最大宽度。获得由存储器输出的数据信号的中心参考电压，并且获得中心参考电压的两个交叉点与数据信号的第二波形的左边缘和右边缘之间的数据宽度。确定数据宽度和最大宽度之间的差异是否大于阈值？如果差值大于阈值，则确定存储器被损坏。

9. 发明申请

US20150092506A1 METHOD AND APPARATUS FOR TESTING MEMORY 有权
标题翻译：测试记忆的方法和装置
公开(公告)号：US20150092506A1
公开(公告)日：2015-04-02
申请号：US14150783
申请日：2014-01-09
申请人： Wistron Corporation
发明人： Min-Hua Hsieh
IPC分类号： G11C29/04
CPC分类号： G11C29/56012 , G11C29/50012 , G11C2029/0407
摘要： A method and an apparatus for testing a memory are provided, and the method is adapted for an electronic apparatus to test the memory. In the method, a left edge and a right edge of a first waveform of a clock signal for testing the memory are scanned to obtain a maximum width between two cross points of the left edge and the right edge. A central reference voltage of a data signal outputted by the memory is obtained, and a data width between two cross points of the central reference voltage and a left edge and a right edge of a second waveform of the data signal is obtained. Whether a difference between the data width and the maximum width is greater than a threshold is determined; if the difference is greater than the threshold, the memory is determined to be damaged.
摘要翻译：提供了一种用于测试存储器的方法和装置，并且该方法适用于电子设备来测试存储器。在该方法中，扫描用于测试存储器的时钟信号的第一波形的左边缘和右边缘，以获得左边缘和右边缘的两个交叉点之间的最大宽度。获得由存储器输出的数据信号的中心参考电压，并且获得中心参考电压的两个交叉点与数据信号的第二波形的左边缘和右边缘之间的数据宽度。确定数据宽度和最大宽度之间的差异是否大于阈值？如果差值大于阈值，则确定存储器被损坏。

10. 发明申请

US20150091110A1 Perpendicular Spin Transfer Torque Memory (STTM) Device with Coupled Free Magnetic Layers 审中-公开
标题翻译：具有耦合自由磁性层的垂直自旋转移转矩存储器（STTM）装置
公开(公告)号：US20150091110A1
公开(公告)日：2015-04-02
申请号：US14039668
申请日：2013-09-27
申请人： Charles C. Kuo , Kaan Oguz , Mark L. Doczy , Brian S. Doyle , Satyarth Suri , Robert S. Chau , David L. Kencke , Roksana Golizadeh Mojarad , Anurag Chaudhry
发明人： Charles C. Kuo , Kaan Oguz , Mark L. Doczy , Brian S. Doyle , Satyarth Suri , Robert S. Chau , David L. Kencke , Roksana Golizadeh Mojarad , Anurag Chaudhry
IPC分类号： H01L43/02 , H01L43/12
CPC分类号： H01L43/10 , G11C11/161 , G11C29/028 , G11C29/56008 , G11C29/56012 , H01F10/3254 , H01F10/3286 , H01F10/329 , H01L43/08
摘要： Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and damping are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A first free magnetic layer is disposed above the dielectric layer. A second free magnetic layer is magnetically coupled with the first free magnetic layer.
摘要翻译：描述了具有增强的稳定性和阻尼的垂直自旋转移转矩存储器（STTM）装置。例如，用于磁隧道结的材料层堆叠包括固定磁性层。电介质层设置在固定磁性层的上方。第一自由磁性层设置在电介质层的上方。第二自由磁性层与第一自由磁性层磁耦合。

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