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1. 发明申请

US20170345471A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
公开(公告)号：US20170345471A1
公开(公告)日：2017-11-30
申请号：US15678634
申请日：2017-08-16
申请人： SK hynix Inc.
发明人： Dong-Uk LEE , Young-Ju KIM , Keun-Soo SONG
IPC分类号： G11C7/22 , G11C8/18 , G11C7/12 , G11C7/10
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1012 , G11C7/1039 , G11C7/1042 , G11C7/1054 , G11C7/1081 , G11C7/12 , G11C7/22 , G11C8/18 , G11C2207/107
摘要： A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

2. 发明授权

US09767869B2 Memory controller, memory system including the same, and electronic device including the memory system 有权
公开(公告)号：US09767869B2
公开(公告)日：2017-09-19
申请号：US14791356
申请日：2015-07-03
申请人： Samsung Electronics Co., Ltd.
发明人： Hyunil Byun , In Sung Joe , Dong Jae Shin
IPC分类号： H04B10/00 , G11C7/10
CPC分类号： G11C7/1081 , G11C7/1054
摘要： A memory system in accordance with an embodiment of the inventive concept includes a memory controller comprising a controller optical transmission unit photoelectrically-converting a data signal to output a first optical modulation signal and a second optical modulation signal, a first memory device which is optically connected with the memory controller to receive the first optical modulation signal, and a second memory device which is optically connected with the memory controller to receive the second optical modulation signal. The first optical modulation signal and the second optical modulation signal are complementary to each other.

3. 发明申请

US20160141014A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20160141014A1
公开(公告)日：2016-05-19
申请号：US15004060
申请日：2016-01-22
申请人： SK hynix Inc.
发明人： Dong-Uk Lee , Young-Ju Kim , Keun-Soo Song
IPC分类号： G11C7/22 , G11C7/12 , G11C7/10
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1012 , G11C7/1039 , G11C7/1042 , G11C7/1054 , G11C7/1081 , G11C7/12 , G11C7/22 , G11C8/18 , G11C2207/107
摘要： A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.
摘要翻译：一种半导体集成电路，包括垂直堆叠的第一半导体芯片和第二半导体芯片，其中，所述第一半导体芯片包括第一列数据驱动电路，其被配置为以基于以下的DDR（双倍数据速率）方案将内部数据传输到所述第二半导体芯片内部选通信号和第一列选通信号驱动电路，被配置为基于内部选通信号产生与由第一列数据驱动电路发送到第二半导体芯片的第一列数据源同步的第一列选通信号，并将第一列选通信号发送到第二半导体芯片。

4. 发明授权

US09047966B2 Architecture of magneto-resistive memory device 有权
标题翻译：磁阻存储器件的架构
公开(公告)号：US09047966B2
公开(公告)日：2015-06-02
申请号：US13931275
申请日：2013-06-28
申请人： Samsung Electronics Co., Ltd.
发明人： Jae-Young Lee , Bong-Jin Kang , Jung-Hwa Hwang , Ki-Woong Yeom , Young-Kwan Kim , Dong-Hyun Shon
IPC分类号： G11C7/00 , G11C11/16 , G11C7/10
CPC分类号： G11C11/1653 , G11C7/1054 , G11C7/1081 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： Provided is a semiconductor memory device including a column decoder, a plurality of sub-cell blocks, and a bit line selection circuit. The column decoder is configured to decode column addresses and drive column selection signals. Each of the sub-cell blocks includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to the plurality of bit lines and the plurality of word lines. The bit line selection circuit includes a plurality of bit line connection controllers, and is configured to select one or more bit lines in response to the column selection signals. Each of the bit line connection controllers electrically couples a respective first bit line to corresponding first and second local input/output (I/O) lines in response to first and second column selection signals of the column selection signals, respectively.
摘要翻译：提供了包括列解码器，多个子单元块和位线选择电路的半导体存储器件。列解码器被配置为解码列地址并驱动列选择信号。每个子单元块包括多个位线，多个字线和连接到多个位线和多个字线的多个存储单元。位线选择电路包括多个位线连接控制器，并且被配置为响应于列选择信号选择一个或多个位线。每个位线连接控制器分别响应于列选择信号的第一和第二列选择信号将相应的第一位线电耦合到相应的第一和第二本地输入/输出（I / O）线。

5. 发明申请

US20130093473A1 DATA OUTPUT APPARATUS AND METHOD FOR OUTPUTTING DATA THEREOF 有权
公开(公告)号：US20130093473A1
公开(公告)日：2013-04-18
申请号：US13692685
申请日：2012-12-03
申请人： SK Hynix Inc.
发明人： Ho-Uk Song
IPC分类号： H03K3/00
CPC分类号： H03K3/00 , G11C7/1051 , G11C7/1054
摘要： A data output apparatus includes a driver driving unit configured to generate driving signals by using input data when a data output enable signal is enabled, a data driver unit configured to drive an output terminal to a level corresponding to the input data in response to the driving signals to generate output data, and an output data level control unit configured to open a current path to control a level of the output data, wherein the current path is different from a current path for driving the output terminal to a level corresponding to the input data.

6. 发明授权

US08295071B2 Apparatus and methods for optically-coupled memory systems 失效
标题翻译：用于光耦合存储器系统的装置和方法
公开(公告)号：US08295071B2
公开(公告)日：2012-10-23
申请号：US13233580
申请日：2011-09-15
申请人： Terry R. Lee , Kevin J. Ryan
发明人： Terry R. Lee , Kevin J. Ryan
IPC分类号： G11C5/06
CPC分类号： G11C7/1054 , G11C7/1051 , G11C7/1078 , G11C7/1081
摘要： Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module.
摘要翻译：公开了光耦合存储器系统。在一个实施例中，系统存储器包括载体衬底和附接到载体衬底并可操作以发射和接收光信号的控制器以及第一和第二存储器模块。第一存储器模块的模块衬底具有形成在其中的孔，该孔可操作以为控制器和第二存储器模块的光发射器/接收器单元之间的光信号提供光路。

7. 发明授权

US07382639B2 System and method for optically interconnecting memory devices 有权
标题翻译：用于光学互连存储器件的系统和方法
公开(公告)号：US07382639B2
公开(公告)日：2008-06-03
申请号：US11542337
申请日：2006-10-02
申请人： George R. Taylor
发明人： George R. Taylor
IPC分类号： G11C5/06
CPC分类号： G11C7/1054 , G11C5/06 , G11C5/063 , G11C7/02 , G11C7/1006 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1081 , G11C7/1096 , H01L2224/16 , H01L2924/00014 , H01L2924/01055 , H01L2924/3025 , H01L2224/0401
摘要： A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable to receive and convert optical address and control signals, respectively, into corresponding electrical address signals applied to the address decoder and control signals applied to the control logic. A read/write circuit on the substrate is coupled to a data converter formed in the substrate. The data converter is operable to receive and convert optical write data signals into corresponding electrical data signals to be applied to the read/write circuit and to receive and convert electrical read data signals into corresponding optical read data signals.
摘要翻译：存储器件包括其中已经制造存储器电路的半导体衬底。地址转换器和控制信号转换器分别耦合到地址解码器和控制逻辑。地址和控制转换器可操作以分别将光地址和控制信号分别转换为施加到地址解码器的相应电地址信号和施加到控制逻辑的控制信号。衬底上的读/写电路耦合到形成在衬底中的数据转换器。数据转换器可操作以将光写入数据信号接收并转换成相应的电数据信号，以施加到读/写电路，并将电读取数据信号接收并转换为相应的光读数据信号。

8. 发明申请

US20080077731A1 Memory module with optical interconnect that enables scalable high-bandwidth memory access 有权
标题翻译：具有光学互连的内存模块，实现可扩展的高带宽内存访问
公开(公告)号：US20080077731A1
公开(公告)日：2008-03-27
申请号：US11526219
申请日：2006-09-22
申请人： Craig S. Forrest , Ashok V. Krishnamoorthy
发明人： Craig S. Forrest , Ashok V. Krishnamoorthy
IPC分类号： G06F12/00
CPC分类号： G11C7/10 , G11C5/04 , G11C7/1051 , G11C7/1054 , G11C7/1078 , G11C7/1081
摘要： One embodiment of the present invention provides a system that facilitates scalable high-bandwidth memory access using a memory module with optical interconnect. This system includes an optical channel, a memory buffer, and a random-access memory module. The memory buffer is configured to receive a request from a memory controller via the optical channel. The memory buffer handles the received request by performing operations on the random-access memory module and then sending a response to the memory controller via the optical channel. Hence, the memory module with optical interconnect provides a high-speed serial link to the random-access memory module without consuming a large number of pins per channel on the memory controller.
摘要翻译：本发明的一个实施例提供一种使用具有光学互连的存储器模块来促进可扩展的高带宽存储器访问的系统。该系统包括光通道，存储器缓冲器和随机存取存储器模块。存储器缓冲器被配置为经由光通道从存储器控制器接收请求。存储器缓冲器通过对随机存取存储器模块执行操作然后经由光信道向存储器控制器发送响应来处理接收到的请求。因此，具有光学互连的存储器模块提供了到随机存取存储器模块的高速串行链路，而不消耗存储器控制器上的每个通道的大量引脚。

9. 发明申请

US20050243590A1 Apparatus and methods for optically-coupled memory systems 失效
公开(公告)号：US20050243590A1
公开(公告)日：2005-11-03
申请号：US11153722
申请日：2005-06-14
申请人： Terry Lee , Kevin Ryan
发明人： Terry Lee , Kevin Ryan
IPC分类号： G02B6/255 , G11C5/06 , G11C7/10 , G11C8/02 , H01L29/22 , H01L31/109
CPC分类号： G11C7/1054 , G11C7/1051 , G11C7/1078 , G11C7/1081
摘要： Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module. Thus, the system memory provides the advantages of “free space” optical connection in a compact arrangement of memory modules. In an alternate embodiment, the first memory module includes a beam splitter attached to the module substrate proximate the aperture. In another embodiment, the first and second memory modules are staged on the carrier substrate to provide an unobstructed path for optical signals. In another embodiment, the optical transmitter/receiver unit projects outwardly from the module substrate to provide an unobstructed path for optical signals.

10. 发明授权

US09190128B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09190128B2
公开(公告)日：2015-11-17
申请号：US14487974
申请日：2014-09-16
申请人： SK hynix Inc.
发明人： Ga-Ram Park , Jae-Il Kim
IPC分类号： G11C7/00 , G11C7/22 , G11C7/10
CPC分类号： G11C7/22 , G11C7/02 , G11C7/1054 , G11C7/106 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C2207/107
摘要： A semiconductor device includes a first buffer suitable for receiving and buffering data, a second buffer suitable for receiving and buffering a data strobe signal, a strobe line suitable for transferring the data strobe signal; a plurality of data transfer lines suitable for transferring data inputted at corresponding turns among data inputted in series through the first buffer, a latch signal generation block suitable for generating a plurality of latch signals which are sequentially activated, based on the data strobe signal transferred through the strobe line, a data latch block suitable for latching and aligning in parallel the data inputted in series through the first buffer, based on the latch signals, and a data transfer block suitable for transferring the data latched by the data latch block to the plurality of data transfer lines, according to a correspondence relationship determined based on an input start signal that is activated at a time when the input of data corresponding to the data input command is started.
摘要翻译：半导体器件包括适于接收和缓冲数据的第一缓冲器，适于接收和缓冲数据选通信号的第二缓冲器，适于传送数据选通信号的选通线; 多个数据传输线路，适于传送通过第一缓冲器串行输入的数据中相应的匝数输入的数据;锁存信号产生块，适于产生依次激活的多个锁存信号，基于通过选通线，一个数据锁存块，适用于基于锁存信号并行地并联串行输入的数据;以及数据传输块，适用于将由数据锁存块锁存的数据传送到多个根据在对应于数据输入命令的数据的输入开始时激活的输入开始信号确定的对应关系。

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