专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08945403B2 Material test structure 有权
标题翻译：材料试验结构
公开(公告)号：US08945403B2
公开(公告)日：2015-02-03
申请号：US13458048
申请日：2012-04-27
申请人： Fabio Pellizzer , Innocenzo Tortorelli , Christina Papagianni , Gianpaolo Spadini , Jong Won Lee
发明人： Fabio Pellizzer , Innocenzo Tortorelli , Christina Papagianni , Gianpaolo Spadini , Jong Won Lee
IPC分类号： H01B13/00
CPC分类号： G01N27/04 , H01L22/34 , H01L43/10 , H01L45/04 , H01L45/06 , H01L45/14 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148
摘要： Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test structure includes forming a number of electrode portions in a first dielectric material, forming a second dielectric material on the first dielectric material, wherein the second dielectric material includes a first cantilever portion and a second cantilever portion, and forming a test material on the number of electrode portions, the first dielectric material, and the second dielectric material.
摘要翻译：本文描述了具有悬臂部分的材料测试结构及其形成方法。作为示例，形成材料测试结构的方法包括在第一介电材料中形成多个电极部分，在第一电介质材料上形成第二电介质材料，其中第二电介质材料包括第一悬臂部分和第二悬臂并且在电极部分，第一介电材料和第二介电材料的数量上形成测试材料。

2. 发明授权

US08921196B2 Double patterning method for creating a regular array of pillars with dual shallow trench isolation 有权
标题翻译：双重图案化方法，用于创建具有双浅沟槽隔离的规则的柱状阵列
公开(公告)号：US08921196B2
公开(公告)日：2014-12-30
申请号：US13132602
申请日：2008-12-30
申请人： Fabio Pellizzer , Marcello Mariani , Giorgio Servalli
发明人： Fabio Pellizzer , Marcello Mariani , Giorgio Servalli
IPC分类号： H01L27/102 , H01L27/24 , H01L21/033 , H01L45/00
CPC分类号： H01L27/2463 , H01L21/0338 , H01L21/76224 , H01L27/1022 , H01L27/2445 , H01L29/0649 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A method is disclosed for forming vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a width below the minimum lithographical resolution F of the lithographic technique employed. In an embodiment, the pillar array features have a dimension of approximately F/2, though this dimension could be reduced down to other values compatible with embodiments of the invention. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.
摘要翻译：公开了用于形成垂直双极结晶体管的方法，其包括基本接触柱的规则阵列和具有低于所采用的光刻技术的最小光刻分辨率F的宽度的发射极接触柱。在一个实施例中，柱阵列特征具有大约F / 2的尺寸，尽管该尺寸可以减小到与本发明的实施例相容的其它值。诸如相变存储元件的存储元件可以形成在基底接触柱和发射极接触柱的规则阵列上方。

3. 发明申请

US20130292633A1 ETCH BIAS HOMOGENIZATION 有权
标题翻译： ETCH BIAS均质化
公开(公告)号：US20130292633A1
公开(公告)日：2013-11-07
申请号：US13463245
申请日：2012-05-03
申请人： Fabio Pellizzer , Hernan A. Castro , Eddie T. Flores
发明人： Fabio Pellizzer , Hernan A. Castro , Eddie T. Flores
IPC分类号： H01L45/00 , H01L21/82 , H01L21/8239
CPC分类号： H01L45/1273 , H01L21/32134 , H01L21/76838 , H01L27/101 , H01L27/2427 , H01L27/2436 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof. Each respective level of conductive material electrically coupled to corresponding circuitry on the substrate is patterned.
摘要翻译：提供了使用蚀刻偏压均化形成的方法和存储器件。使用蚀刻偏压均化形成存储器件的一个示例性方法包括在衬底上形成相应电平的导电材料。在对相应级别的导电材料进行图案化期间，每个相应级别的导电材料电耦合到衬底上的对应电路，使得每个相应级别的导电材料在其图案化期间具有均质化的蚀刻偏压。电耦合到衬底上的对应电路的每个相应级别的导电材料被图案化。

4. 发明申请

US20130283936A1 MATERIAL TEST STRUCTURE 有权
公开(公告)号：US20130283936A1
公开(公告)日：2013-10-31
申请号：US13458048
申请日：2012-04-27
申请人： Fabio Pellizzer , Innocenzo Tortorelli , Christina Papagianni , Gianpaolo Spadini , Jong Won Lee
发明人： Fabio Pellizzer , Innocenzo Tortorelli , Christina Papagianni , Gianpaolo Spadini , Jong Won Lee
IPC分类号： G01N33/00 , H01B13/00 , C23C16/455 , B05D5/12
CPC分类号： G01N27/04 , H01L22/34 , H01L43/10 , H01L45/04 , H01L45/06 , H01L45/14 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148
摘要： Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test structure includes forming a number of electrode portions in a first dielectric material, forming a second dielectric material on the first dielectric material, wherein the second dielectric material includes a first cantilever portion and a second cantilever portion, and forming a test material on the number of electrode portions, the first dielectric material, and the second dielectric material.

5. 发明授权

US08536013B2 Forming phase change memory cells 有权
标题翻译：形成相变存储单元
公开(公告)号：US08536013B2
公开(公告)日：2013-09-17
申请号：US13114966
申请日：2011-05-24
申请人： Yudong Kim , Fabio Pellizzer
发明人： Yudong Kim , Fabio Pellizzer
IPC分类号： H01L21/62
CPC分类号： H01L45/06 , H01L27/2445 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1691
摘要： Small phase change memory cells may be formed by forming a segmented heater over a substrate. A stop layer may be formed over the heater layer and segmented with the heater layer. Then, sidewall spacers may be formed over the segmented heater to define an aperture between the sidewall spacers that may act as a mask for etching the stop layer over the segmented heater. As a result of the etching using the sidewall spacers as a mask, sublithographic pore may be formed over the heater. Phase change material may be formed within the pore.
摘要翻译：可以通过在衬底上形成分段加热器来形成小相变存储器单元。停止层可以形成在加热器层上并且与加热器层分段。然后，侧壁间隔物可以形成在分段加热器上方，以在侧壁间隔物之间形成孔，其可用作蚀刻分段加热器上的停止层的掩模。作为使用侧壁间隔物作为掩模的蚀刻的结果，可以在加热器上形成亚光刻孔。相变材料可以在孔内形成。

6. 发明申请

US20130207068A1 MEMORY CELLS AND MEMORY CELL FORMATION METHODS USING SEALING MATERIAL 有权
公开(公告)号：US20130207068A1
公开(公告)日：2013-08-15
申请号：US13369654
申请日：2012-02-09
申请人： Fabio Pellizzer
发明人： Fabio Pellizzer
IPC分类号： H01L27/24 , H01L21/62
CPC分类号： H01L45/16 , H01L27/2427 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/1675
摘要： Memory cells, arrays of memory cells, and methods of forming the same with sealing material on sidewalls thereof are disclosed herein. One example of forming a memory cell includes forming a stack of materials, forming a trench to a first depth in the stack of materials such that a portion of at least one of the active storage element material and the active select device material is exposed on sidewalls of the trench. A sealing material is formed on the exposed portion of the at least one of the active storage element material and the active select device material and the trench is deepened such that a portion of the other of the at least one of the active storage element material and the active select device material is exposed on the sidewalls of the trench.

7. 发明授权

US08084789B2 Phase change memory with ovonic threshold switch 有权
标题翻译：相位变化记忆体带有超声门限开关
公开(公告)号：US08084789B2
公开(公告)日：2011-12-27
申请号：US12700440
申请日：2010-02-04
申请人： Fabio Pellizzer , Agostino Pirovano
发明人： Fabio Pellizzer , Agostino Pirovano
IPC分类号： H01L29/76
CPC分类号： H01L45/06 , H01L27/2427 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/1675
摘要： A phase change memory includes a memory element and a selection element. The memory element is embedded in a dielectric and includes a resistive element having at least one sublithographic dimension and a storage region in contact with the resistive element. The selection element includes a chalcogenic material embedded in a dielectric. The chalcogenic material and the storage region are part of a stack having a common etched edge.
摘要翻译：相变存储器包括存储元件和选择元件。存储元件嵌入在电介质中，并且包括具有至少一个亚光刻尺寸的电阻元件和与电阻元件接触的存储区域。选择元件包括埋在电介质中的硫属材料。硫属材料和存储区域是具有共同蚀刻边缘的堆叠的一部分。

8. 发明申请

US20110248233A1 METHOD FOR FABRICATING A PHASE-CHANGE MEMORY CELL 有权
标题翻译：制备相变记忆细胞的方法
公开(公告)号：US20110248233A1
公开(公告)日：2011-10-13
申请号：US13132603
申请日：2008-12-30
申请人： Fabio Pellizzer , Michele Magistretti , Cristina Casellato , Monica Vigilante
发明人： Fabio Pellizzer , Michele Magistretti , Cristina Casellato , Monica Vigilante
IPC分类号： H01L45/00
CPC分类号： H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/16 , H01L45/1608 , H01L45/1675
摘要： A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer (228) on a metal layer (226) above a substrate. A phase-change material layer (230) is formed on the dielectric layer. A contact region (232) is formed, within the dielectric layer, between the phase-change material layer and the metal layer by breaking-down a portion of the dielectric layer.
摘要翻译：描述了制造相变存储单元的方法。该方法包括在衬底上的金属层（226）上形成介电层（228）。在介电层上形成相变材料层（230）。通过分解介电层的一部分，在介电层内形成接触区域（232），位于相变材料层和金属层之间。

9. 发明申请

US20110084247A1 Self-Aligned Bipolar Junction Transistors 审中-公开
标题翻译：自对准双极结晶体管
公开(公告)号：US20110084247A1
公开(公告)日：2011-04-14
申请号：US12969652
申请日：2010-12-16
申请人： Fabio Pellizzer , Roberto Bez , Paola Zuliani , Augusto Benvenuti
发明人： Fabio Pellizzer , Roberto Bez , Paola Zuliani , Augusto Benvenuti
IPC分类号： H01L45/00 , H01L27/082
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/1022 , H01L27/24 , H01L29/66272
摘要： A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.
摘要翻译：通过形成公共导电区域，在公共导电区域上的自身有效区域中延伸的多个控制区域，多个硅化物保护带和至少一个控制接触区域来形成多个双极晶体管。在第二导电区域和控制接触区域上形成硅化物区域。可以通过在所选择的硅化物保护条的第一侧选择性地注入第一导电类型的掺杂剂区域来形成第二导电区域。通过在所选择的硅化物保护带的第二侧选择性地注入相反的导电型掺杂剂来形成控制接触区域。

10. 发明授权

US07898848B2 Memory including bipolar junction transistor select devices 有权
标题翻译：存储器包括双极结型晶体管选择器件
公开(公告)号：US07898848B2
公开(公告)日：2011-03-01
申请号：US11788909
申请日：2007-04-23
申请人： Agostino Pirovano , Fabio Pellizzer
发明人： Agostino Pirovano , Fabio Pellizzer
IPC分类号： G11C11/00
CPC分类号： H01L29/735 , G11C13/0004 , G11C13/003 , G11C2213/76 , G11C2213/79 , H01L27/0207 , H01L27/1022 , H01L27/24
摘要： An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions overlying the common region. Each shared control region forms the control regions of a plurality of adjacent selection transistors and accommodates the first regions of the plurality of adjacent selection transistors as well as contact portions of the shared control region. Blocks of adjacent selection transistors of the plurality of selection transistors share a contact portion and the first regions of a block of adjacent selection transistors are arranged along the shared control region between two contact portions. A plurality of biasing structures are formed between pairs of first regions of adjacent selection transistors, for modifying a charge distribution in the shared control region below the biasing structures.
摘要翻译：阵列由多个单元形成，其中每个单元由具有第一，第二和控制区域的双极结选择晶体管形成。单元包括形成选择晶体管的第二区域的公共区域和覆盖在公共区域上的多个共享控制区域。每个共享控制区域形成多个相邻选择晶体管的控制区域并且容纳多个相邻选择晶体管的第一区域以及共享控制区域的接触部分。多个选择晶体管的相邻选择晶体管的块共享接触部分，并且沿着两个接触部分之间的共享控制区域布置相邻选择晶体管的块的第一区域。在相邻选择晶体管的第一区域对之间形成多个偏置结构，用于修改偏置结构下方的共享控制区域中的电荷分布。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式