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1. 发明申请

US20180190667A1 SELECT TRANSISTORS WITH TIGHT THRESHOLD VOLTAGE IN 3D MEMORY 审中-公开
公开(公告)号：US20180190667A1
公开(公告)日：2018-07-05
申请号：US15906317
申请日：2018-02-27
申请人： SanDisk Technologies LLC
发明人： Liang Pang , Jayavel Pachamuthu , Yingda Dong
IPC分类号： H01L27/11519 , H01L21/28 , H01L29/66 , H01L27/11582 , H01L27/1157 , H01L27/11565 , H01L21/02 , H01L27/11556 , H01L27/11524
CPC分类号： H01L27/11519 , H01L21/02532 , H01L21/0262 , H01L21/28273 , H01L21/28282 , H01L27/11524 , H01L27/11553 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/1158 , H01L27/11582 , H01L29/66825 , H01L29/66833
摘要： Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.

2. 发明授权

US09953710B2 Memory devices with a connecting region having a band gap lower than a band gap of a body region 有权
公开(公告)号：US09953710B2
公开(公告)日：2018-04-24
申请号：US15583411
申请日：2017-05-01
申请人： Micron Technology, Inc.
发明人： Haitao Liu , Jian Li , Chandra Mouli
IPC分类号： H01L29/66 , G11C16/14 , H01L27/1158 , H01L27/11582 , H01L29/792 , G11C16/04 , G11C16/10 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/20 , H01L29/22
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/1158 , H01L27/11582 , H01L29/0847 , H01L29/16 , H01L29/161 , H01L29/20 , H01L29/2003 , H01L29/22 , H01L29/7926
摘要： Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

3. 发明授权

US09941293B1 Select transistors with tight threshold voltage in 3D memory 有权
公开(公告)号：US09941293B1
公开(公告)日：2018-04-10
申请号：US15291871
申请日：2016-10-12
申请人： SanDisk Technologies LLC
发明人： Liang Pang , Jayavel Pachamuthu , Yingda Dong
IPC分类号： H01L29/788 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L29/66 , H01L21/02 , H01L21/28 , H01L27/11565 , H01L27/1157 , H01L27/11582
CPC分类号： H01L27/11519 , H01L21/02532 , H01L21/0262 , H01L21/28273 , H01L21/28282 , H01L27/11524 , H01L27/11553 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/1158 , H01L27/11582 , H01L29/66825 , H01L29/66833
摘要： Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.

4. 发明授权

US09640260B2 Memory devices with a connecting region having a band gap lower than a band gap of a body region 有权
公开(公告)号：US09640260B2
公开(公告)日：2017-05-02
申请号：US14320174
申请日：2014-06-30
申请人： Micron Technology, Inc.
发明人： Haitao Liu , Jian Li , Chandra Mouli
IPC分类号： H01L29/66 , G11C16/04 , H01L27/1158 , H01L27/11582 , H01L29/792 , G11C16/10
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/1158 , H01L27/11582 , H01L29/0847 , H01L29/16 , H01L29/161 , H01L29/20 , H01L29/2003 , H01L29/22 , H01L29/7926
摘要： Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

5. 发明申请

US20170069652A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20170069652A1
公开(公告)日：2017-03-09
申请号：US15008554
申请日：2016-01-28
申请人： Kabushiki Kaisha Toshiba
发明人： Shinya ARAI
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/1158 , H01L28/00 , H01L29/788
摘要： According to one embodiment, the stacked body includes a plurality of electrode films stacked with an insulating body. The insulating body includes a first insulating film provided between the electrode films in a region surrounding the columnar portions. A gap is provided between the electrode films in a region on a lateral side in the first direction of the interconnect portion.
摘要翻译：根据一个实施例，堆叠体包括堆叠有绝缘体的多个电极膜。绝缘体包括设置在围绕柱状部分的区域中的电极膜之间的第一绝缘膜。在互连部分的第一方向上的横向侧的区域中的电极膜之间设置有间隙。

6. 发明申请

US20160233343A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160233343A1
公开(公告)日：2016-08-11
申请号：US15017818
申请日：2016-02-08
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Hidekazu MIYAIRI
IPC分类号： H01L29/786 , H01L29/06 , H01L29/423
CPC分类号： H01L29/0688 , H01L27/11273 , H01L27/11553 , H01L27/11556 , H01L27/1158 , H01L27/11582 , H01L29/41733 , H01L29/4236 , H01L29/42384 , H01L29/4908 , H01L29/78642 , H01L29/7869 , H01L29/78696
摘要： A miniaturized transistor having highly stable electrical characteristics is provided. Furthermore, high performance and high reliability of a semiconductor device including the transistor is achieved. The transistor includes a first electrode, a second electrode, a third electrode, an oxide semiconductor layer, a first insulating layer, and a second insulating layer. The transistor includes a first region and a second region surrounded by the first region. In the first region, the first insulating layer, the second electrode, the oxide semiconductor layer, and the second insulating layer are stacked. In the second region, the first electrode, the oxide semiconductor layer, the second insulating layer, and the third electrode are stacked.
摘要翻译：提供具有高度稳定的电气特性的小型化晶体管。此外，实现了包括晶体管的半导体器件的高性能和高可靠性。晶体管包括第一电极，第二电极，第三电极，氧化物半导体层，第一绝缘层和第二绝缘层。晶体管包括由第一区域包围的第一区域和第二区域。在第一区域中，堆叠第一绝缘层，第二电极，氧化物半导体层和第二绝缘层。在第二区域中，堆叠第一电极，氧化物半导体层，第二绝缘层和第三电极。

7. 发明申请

US20160056302A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE 审中-公开
标题翻译：三维半导体器件
公开(公告)号：US20160056302A1
公开(公告)日：2016-02-25
申请号：US14932600
申请日：2015-11-04
申请人： SK hynix Inc.
发明人： Jin Ho BIN , Ki Hong LEE
IPC分类号： H01L29/792 , H01L27/115
CPC分类号： H01L29/7926 , H01L27/1158 , H01L27/11582 , H01L29/66833 , H01L29/78
摘要： A three-dimensional (3D) semiconductor device includes first interlayer dielectric layers and word lines that are alternately stacked on a substrate; select lines formed on the first interlayer dielectric layers and the word lines; etch stop patterns formed on the select lines to contact the select lines; channel holes formed to pass through the select lines, the first interlayer dielectric layers, and the word lines; channel layers formed on surfaces of the channel holes; insulating layers formed in the channel holes, the insulating layers having an upper surface that is lower than upper surfaces of the etch stop patterns; impurity-doped layers formed in channel holes on upper surface of the insulating layers; and a second interlayer dielectric layer formed over the etch stop patterns and the impurity-doped layers.
摘要翻译：三维（3D）半导体器件包括交替堆叠在衬底上的第一层间电介质层和字线; 形成在第一层间电介质层和字线上的选择线; 形成在选择线上以接触选择线的蚀刻停止图案; 形成为通过选择线，第一层间电介质层和字线的通道孔; 通道层形成在通道孔的表面上; 绝缘层形成在通道孔中，绝缘层具有比蚀刻停止图案的上表面低的上表面; 在绝缘层的上表面的通道孔中形成杂质掺杂层; 以及形成在蚀刻停止图案和杂质掺杂层之上的第二层间介电层。

8. 发明申请

US20150380548A1 VERTICAL DEVICE ARCHITECTURE 有权
标题翻译：垂直装置架构
公开(公告)号：US20150380548A1
公开(公告)日：2015-12-31
申请号：US14318835
申请日：2014-06-30
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chih-Hao Wang , Jhon Jhy Liaw , Wai-Yi Lien , Jia-Chuan You , Yi-Hsun Chiu , Ching-Wei Tsai , Wei-Hao Wu
IPC分类号： H01L29/78 , H01L29/10 , H01L29/423 , H01L29/66
CPC分类号： H01L29/7827 , H01L21/8221 , H01L27/0688 , H01L27/1104 , H01L27/11556 , H01L27/1158 , H01L27/11582 , H01L29/66666 , H01L29/7889 , H01L29/7926
摘要： The present disclosure relates to a vertical transistor device having rectangular vertical channel bars extending between a source region and a drain region, and an associated method of formation. In some embodiments, the vertical transistor device has a source region disposed over a semiconductor substrate. A channel region with one or more vertical channel bars is disposed over the source region. The one or more vertical channel bars have a bottom surface abutting the source region that has a rectangular shape (i.e., a shape with four sides, with adjacent sides of different length, and four right angles). A gate region is located over the source region at a position abutting the vertical channel bars, and a drain region is disposed over the gate region and the vertical channel bars. The rectangular shape of the vertical channel bars provides for a vertical device having good performance and cell area density.
摘要翻译：本公开涉及具有在源极区域和漏极区域之间延伸的矩形垂直沟道条的垂直晶体管器件以及相关联的形成方法。在一些实施例中，垂直晶体管器件具有设置在半导体衬底上的源极区域。具有一个或多个垂直通道条的通道区域设置在源极区域上。一个或多个垂直通道杆具有邻接源区域的底表面，该源区域具有矩形形状（即具有四边的形状，具有不同长度的相邻边和四个直角）。栅极区域位于邻近垂直沟道条的位置处的源极区域上方，并且漏极区域设置在栅极区域和垂直沟道条的上方。垂直通道条的矩形形状提供具有良好性能和单元面积密度的垂直装置。

9. 发明授权

US09158622B2 Storage device including non-volatile memory device and repair method 有权
标题翻译：存储设备包括非易失性存储设备和修复方法
公开(公告)号：US09158622B2
公开(公告)日：2015-10-13
申请号：US13784874
申请日：2013-03-05
申请人： Joonho Lee , Jong-Nam Baek , Dong-Hoon Ham , Sang-Wook Yoo , Intae Hwang
发明人： Joonho Lee , Jong-Nam Baek , Dong-Hoon Ham , Sang-Wook Yoo , Intae Hwang
IPC分类号： G11C29/00 , G06F11/10 , G06F11/16 , H01L27/115 , G06F12/02 , G06F11/14 , G11C16/10 , G06F11/20
CPC分类号： G06F11/1068 , G06F11/1402 , G06F11/1415 , G06F11/1666 , G06F11/20 , G06F12/0246 , G06F2212/7209 , G11C16/105 , G11C29/785 , G11C29/808 , G11C29/82 , H01L27/1158
摘要： Disclosed is a storage device which includes a nonvolatile memory device including a memory block a program order of which is adjusted regardless of an arrangement of memory cells, and a memory controller that performs address mapping to replace a bad page of the memory block with a normal page of the memory block.
摘要翻译：公开了一种存储装置，其包括非易失性存储装置，其包括不管存储器单元的布置而调整其程序顺序的存储块;以及存储器控制器，其执行地址映射以用正常代替存储块的坏页内存块的页面。

10. 发明授权

US09070581B2 Vertical-type semiconductor devices and methods of manufacturing the same 有权
标题翻译：垂直型半导体器件及其制造方法
公开(公告)号：US09070581B2
公开(公告)日：2015-06-30
申请号：US14083971
申请日：2013-11-19
申请人： Samsung Electronics Co., Ltd.
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L21/336 , H01L27/105 , H01L27/115 , H01L29/66 , H01L29/792
CPC分类号： H01L27/11582 , H01L21/02524 , H01L21/02587 , H01L21/02598 , H01L21/02675 , H01L21/28282 , H01L21/28518 , H01L21/30604 , H01L21/32133 , H01L27/1052 , H01L27/11568 , H01L27/11578 , H01L27/1158 , H01L29/4234 , H01L29/45 , H01L29/665 , H01L29/66666 , H01L29/66787 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.
摘要翻译：在垂直型存储器件和垂直型存储器件的制造方法中，垂直存储器件包括设置在衬底上的线状绝缘层图形，柱状单晶半导体图案设置在两侧壁上设置在每个单晶半导体图案的侧壁上的绝缘层图案和晶体管。晶体管沿着单晶半导体图案的垂直方向排列，因此存储器件可以高度集成。

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