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1. 发明申请

US20190245034A1 POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE 审中-公开
公开(公告)号：US20190245034A1
公开(公告)日：2019-08-08
申请号：US16387243
申请日：2019-04-17
申请人： Silanna Asia Pte Ltd
发明人： Jacek Korec , Boyi Yang
IPC分类号： H01L29/06 , H01L27/06 , H01L29/78 , H01L29/872 , H01L21/8234 , H01L27/088 , H01L29/40 , H01L29/49 , H01L29/66 , H01L29/10 , H01L29/36 , H01L29/423 , H01L29/73 , H01L29/735 , H01L29/8605 , H01L29/861 , H01L29/94 , H01L21/8249
CPC分类号： H01L29/0626 , H01L21/823437 , H01L21/8249 , H01L27/0629 , H01L27/0635 , H01L27/088 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/36 , H01L29/402 , H01L29/41766 , H01L29/42304 , H01L29/4236 , H01L29/4933 , H01L29/66181 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66704 , H01L29/7302 , H01L29/735 , H01L29/78 , H01L29/7821 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/8605 , H01L29/861 , H01L29/872 , H01L29/94 , H01L2224/0401 , H01L2224/05552 , H01L2224/05569 , H01L2224/05572 , H01L2224/11 , H01L2224/13 , H01L2924/00 , H01L2924/00014 , H01L2924/12032 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091
摘要： A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

2. 发明申请

US20190181134A1 BACK BALLASTED VERTICAL NPN TRANSISTOR 审中-公开
公开(公告)号：US20190181134A1
公开(公告)日：2019-06-13
申请号：US15838876
申请日：2017-12-12
申请人： Texas Instruments Incorporated
发明人： Akram Ali Salman , Guruvayurappan Mathur , Ryo Tsukahara
IPC分类号： H01L27/02 , H01L29/73 , H01L29/08 , H01L27/06 , H01L29/66
CPC分类号： H01L27/0262 , H01L27/0259 , H01L27/0623 , H01L29/0646 , H01L29/0804 , H01L29/0821 , H01L29/66234 , H01L29/66287 , H01L29/7302 , H01L29/7304
摘要： Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.

3. 发明申请

US20180033783A1 Avalanche Diode Having an Enhanced Defect Concentration Level and Method of Making the Same 审中-公开
公开(公告)号：US20180033783A1
公开(公告)日：2018-02-01
申请号：US15782582
申请日：2017-10-12
申请人： Infineon Technologies AG
发明人： Jens Schneider , Kai Esmark , Martin Wendel
IPC分类号： H01L27/02 , H01L21/322 , H01L29/866 , H01L29/73 , H01L29/66 , H01L21/265 , H01L29/06 , H01L29/32 , H01L29/861 , H01L23/62
CPC分类号： H01L27/0255 , H01L21/26506 , H01L21/3221 , H01L23/62 , H01L27/0259 , H01L29/0603 , H01L29/32 , H01L29/66113 , H01L29/7302 , H01L29/861 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.

4. 发明授权

US09666700B2 Vertical bipolar junction transistor and manufacturing method thereof 有权
公开(公告)号：US09666700B2
公开(公告)日：2017-05-30
申请号：US14525545
申请日：2014-10-28
申请人： MagnaChip Semiconductor, Ltd.
发明人： Francois Hebert , Yon Sup Pang , Seong Min Cho , Ju Ho Kim
IPC分类号： H01L29/732 , H01L29/73 , H01L29/423 , H01L29/66 , H01L29/08 , H01L29/10 , H01L29/78 , H01L21/8249
CPC分类号： H01L29/732 , H01L21/8249 , H01L29/0821 , H01L29/10 , H01L29/1083 , H01L29/1095 , H01L29/423 , H01L29/66272 , H01L29/7302 , H01L29/7816 , H01L29/7835
摘要： The present disclosure relates to a vertical bipolar junction transistor. A vertical bipolar junction transistor includes a high concentration doping region emitter terminal disposed on a semiconductor substrate; a high concentration doping region collector terminal disposed on a semiconductor substrate; a high concentration doping region base terminal disposed between the emitter terminal and the collector terminal; a drift region having a first doping concentration surrounding the emitter terminal and being deeper than either the base terminal or the collector terminal; a base layer disposed below the drift region; a collector layer in contact with the base layer, the collector layer having a second doping concentration higher than the first doping concentration. The manufacturing cost of the vertical bipolar junction transistor can be lowered and a current gain can be elevated using a low-cost BCD process.

5. 发明授权

US09508777B2 Hybrid bipolar junction transistor 有权
公开(公告)号：US09508777B2
公开(公告)日：2016-11-29
申请号：US14827266
申请日：2015-08-14
申请人： International Business Machines Corporation
发明人： Ali Afzali-Ardakani , Bahman Hekmatshoartabari , Tak H. Ning , Davood Shahrjerdi
IPC分类号： H01L27/32 , H01L27/12 , H01L29/08 , H01L29/10 , H01L29/73 , H01L29/66
CPC分类号： H01L27/286 , H01L27/1214 , H01L27/124 , H01L27/3225 , H01L27/3244 , H01L27/3274 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/66265 , H01L29/7302 , H01L29/7317 , H01L51/0055 , H01L51/0504 , H01L2227/323
摘要： Bipolar junction transistors including inorganic channels and organic emitter junctions are used in some applications for forming high resolution active matrix displays. Arrays of such bipolar junction transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.

6. 发明授权

US09425190B2 Techniques for providing a direct injection semiconductor memory device 有权
公开(公告)号：US09425190B2
公开(公告)日：2016-08-23
申请号：US14503784
申请日：2014-10-01
申请人： Micron Technology, Inc.
发明人： Yogesh Luthra , Serguei Okhonin , Mikhail Nagoga
IPC分类号： G11C16/10 , H01L27/06 , G11C5/02 , G11C5/06 , G11C8/08 , G11C8/10 , G11C11/4074 , G11C11/4094 , G11C7/00 , H01L29/73 , H01L29/732
CPC分类号： H01L27/0664 , G11C5/025 , G11C5/06 , G11C5/063 , G11C7/00 , G11C8/08 , G11C8/10 , G11C11/4074 , G11C11/4094 , G11C2211/4016 , H01L29/7302 , H01L29/732
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.

7. 发明申请

US20160204779A1 Operating Point Optimization with Double-Base-Contact Bidirectional Bipolar Junction Transistor Circuits, Methods, and Systems 有权
标题翻译：双基接触双向晶体管电路，方法和系统的工作点优化
公开(公告)号：US20160204779A1
公开(公告)日：2016-07-14
申请号：US14935349
申请日：2015-11-06
申请人： Ideal Power Inc.
发明人： William C. Alexander
IPC分类号： H03K17/66
CPC分类号： H03K17/66 , H01L27/0694 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/1095 , H01L29/7302 , H01L29/732 , H01L29/735 , H01L29/7412 , H01L29/7416 , H01L29/747 , H01L29/872 , H02M1/08 , H02M7/219 , H02M2007/2195 , H03K17/60 , H03K17/602 , H03K17/687 , H03K2217/0054
摘要： The present application teaches, among other innovations, methods and circuits for operating a B-TRAN (double-base bidirectional bipolar junction transistor). A base drive circuit is described which provides high-impedance drive to the base contact region on whichever side of the device is operating as the collector (at a given moment). (The B-TRAN, unlike other bipolar junction transistors, is controlled by applied voltage rather than applied current.) The preferred implementation of the drive circuit is operated by control signals to provide diode-mode turn-on and pre-turnoff operation, as well as a hard ON state with a low voltage drop (the “transistor-ON” state). In some but not necessarily all preferred embodiments, an adjustable low voltage for the gate drive circuit is provided by a self-synchronizing rectifier circuit. Also, in some but not necessarily all preferred embodiments, the base drive voltage used to drive the c-base region (on the collector side) is varied while the base current at that terminal is monitored, so that no more base current than necessary is applied. This solves the difficult challenge of optimizing base drive in a B-TRAN.
摘要翻译：除了其他创新之外，本申请教导了用于操作B-TRAN（双基极双极结型晶体管）的方法和电路。描述了一种基本驱动电路，其在设备的任何一侧作为收集器（在给定时刻）提供对基底接触区域的高阻抗驱动。（B-TRAN与其他双极结型晶体管不同，由施加的电压而不是施加的电流控制。）驱动电路的优选实现由控制信号操作，以提供二极管模式导通和预关断操作，如以及具有低电压降（“晶体管接通”状态）的硬导通状态。在一些但不一定所有的优选实施例中，栅极驱动电路的可调低电压由自同步整流电路提供。此外，在一些但不一定所有优选实施例中，用于驱动c-基极区域（集电极侧）的基极驱动电压在监测该端子处的基极电流的同时被改变，使得不再需要基极电流应用。这解决了在B-TRAN中优化基础驱动的困难挑战。

8. 发明授权

US09356012B2 High voltage ESD protection apparatus 有权
标题翻译：高压ESD保护装置
公开(公告)号：US09356012B2
公开(公告)日：2016-05-31
申请号：US13243688
申请日：2011-09-23
申请人： Yi-Feng Chang , Jam-Wem Lee
发明人： Yi-Feng Chang , Jam-Wem Lee
IPC分类号： H01L27/02
CPC分类号： H01L27/0259 , H01L23/50 , H01L27/0255 , H01L27/067 , H01L29/0649 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/7302
摘要： An ESD protection apparatus comprises a metal contact formed on the emitter of a transistor. The metal contact has a different conductivity type from the emitter. In addition, the metal contact and the emitter of the transistor form a diode connected in series with the transistor. The diode connected in series with the transistor provides extra headroom for the breakdown voltage of the ESD protection apparatus.
摘要翻译： ESD保护装置包括形成在晶体管的发射极上的金属触点。金属触点具有与发射极不同的导电类型。此外，晶体管的金属接触和发射极形成与晶体管串联连接的二极管。与晶体管串联连接的二极管为ESD保护装置的击穿电压提供了额外的余量。

9. 发明申请

US20160086954A1 Memory Device Having Electrically Floating Body Transistor 有权
公开(公告)号：US20160086954A1
公开(公告)日：2016-03-24
申请号：US14955339
申请日：2015-12-01
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja , Jin-Woo Han , Benjamin S. Louie
IPC分类号： H01L27/108 , H01L29/08 , H01L29/73 , H01L29/10 , H01L29/78 , H01L27/102
CPC分类号： H01L27/10802 , G11C11/404 , G11C16/0433 , G11C16/10 , G11C16/26 , G11C16/3427 , H01L27/1023 , H01L27/11524 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/1095 , H01L29/36 , H01L29/70 , H01L29/73 , H01L29/7302 , H01L29/732 , H01L29/7841
摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

10. 发明授权

US09276060B2 Triode 有权
标题翻译：三极管
公开(公告)号：US09276060B2
公开(公告)日：2016-03-01
申请号：US14497778
申请日：2014-09-26
申请人： Fitipower Integrated Technology, Inc.
发明人： Chih-Nan Cheng
IPC分类号： H01L29/74 , H01L29/06 , H01L29/73 , H01L29/747
CPC分类号： H01L29/0607 , H01L29/7302 , H01L29/747
摘要： A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region via at least one conducting channel.
摘要翻译：三极管包括半导体，深n阱，p阱，n +掺杂区和掺杂区。深n阱邻近半导体衬底设置。 p阱包含在深n阱中，并用作三极管的集电极区域。 n +掺杂区域用作三极管的基极区域。 p +掺杂区域用作三极管的发射极区域。深n阱经由至少一个导电沟道耦合到n +掺杂区域。

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