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1. 发明授权

US09735765B2 Apparatuses, methods, and systems for jitter equalization and phase error detection 有权
公开(公告)号：US09735765B2
公开(公告)日：2017-08-15
申请号：US15019764
申请日：2016-02-09
申请人： Intel Corporation
发明人： Nicholas P. Cowley , Chi Man Kan , Ruchir Saraswat
IPC分类号： H04B3/46 , H03K5/13 , H04L1/20 , H03D13/00 , H04B3/14 , H03L7/097 , H03K5/00
CPC分类号： H03K5/13 , H03D13/003 , H03K2005/00019 , H03L7/097 , H04B3/146 , H04L1/205
摘要： Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.

2. 发明授权

US08648632B2 Digital PLL circuit, semiconductor integrated circuit, and display apparatus 有权
标题翻译：数字PLL电路，半导体集成电路和显示装置
公开(公告)号：US08648632B2
公开(公告)日：2014-02-11
申请号：US13313638
申请日：2011-12-07
申请人： Hiroki Mouri , Kouji Okamoto , Fumiaki Senoue
发明人： Hiroki Mouri , Kouji Okamoto , Fumiaki Senoue
IPC分类号： H03L7/06
CPC分类号： H03D13/003 , H03L7/087 , H03L2207/50
摘要： In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time period, and detects, as a phase error value, a difference between a target count value, obtained based on a magnification value of a desired oscillating frequency with respect to the frequency of the reference clock and the reference count value, and the number of transitions of the oscillation clock in the phase comparison time period. A smoothing circuit smoothes the phase error value. A digitally-controlled oscillation circuit controls the frequency of the oscillation clock in accordance with the phase error value smoothed by the smoothing circuit.
摘要翻译：在数字PLL电路中，相位比较电路对参考时钟和振荡时钟的转换次数进行计数，将所参考时钟的转换次数达到参考计数值所花费的时间设置为相位比较时间段，以及将作为相位误差值的目标计数值相对于基准时钟的频率和基准计数值的期望的振荡频率的倍率值与振荡的转移次数进行比较，时钟在相位比较时间段。平滑电路平滑相位误差值。数字控制振荡电路根据平滑电路平滑的相位误差值来控制振荡时钟的频率。

3. 发明授权

US07804926B2 PLL using unbalanced quadricorrelator 失效
标题翻译： PLL使用不平衡二次相关器
公开(公告)号：US07804926B2
公开(公告)日：2010-09-28
申请号：US10533058
申请日：2003-10-08
申请人： Mihai Adrian Tiberiu Sanduleanu
发明人： Mihai Adrian Tiberiu Sanduleanu
IPC分类号： H03D3/24
CPC分类号： H03L7/087 , H03D13/003 , H03L7/091 , H03L2207/06 , H04L7/0274
摘要： A Phase Locked Loop (1) used in a data and clock recovery comprising a frequency detector (10) including a quadricorrelator (2), the quadricorrelator (2) comprising a frequency detector including double edge clocked bi-stable circuits (21, 22, 23, 24) coupled to a first multiplexer (31) and to a second multiplexer (32) being controlled by a signal having a same bitrate as the incoming signal (D), and a phase detector (DFF) controlled by a first signal pair (PQ, PQ provided by the first multiplexer (31) and by a second signal pair (PI, PI) provided by the second multiplexer (32).
摘要翻译：一种用于数据和时钟恢复的锁相环（1），包括包括二次相关器（2）的频率检测器（10），所述四相关器（2）包括频率检测器，所述频率检测器包括双边沿时钟双稳态电路（21,22，耦合到第一多路复用器（31）的第二多路复用器（32）和由具有与输入信号（D）相同的比特率的信号控制的第二多路复用器（32），以及由第一信号对（D）控制的相位检测器（PQ，PQ由第一多路复用器31提供）和由第二多路复用器（32）提供的第二信号对（PI，PI）。

4. 发明授权

US07769121B2 Phase detector for data communications 有权
标题翻译：用于数据通信的相位检测器
公开(公告)号：US07769121B2
公开(公告)日：2010-08-03
申请号：US11315029
申请日：2005-12-22
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03D13/003 , H03L7/0891 , H03L7/091
摘要： In one embodiment, a phase error signal generated by a phase detector is equalized to compensate for the distortion in the phase error signal due to finite circuit speeds. The equalization may be based on suppressing the low frequency components of the phase error signal. For example, the amplitude of the phase error signal may be reduced when the amplitude of the phase error signal is not changing.
摘要翻译：在一个实施例中，由相位检测器产生的相位误差信号被均衡以补偿由于有限电路速度引起的相位误差信号中的失真。均衡可以基于抑制相位误差信号的低频分量。例如，当相位误差信号的振幅不变时，相位误差信号的幅度可能会降低。

5. 发明授权

US07643599B2 Method and apparatus for detecting linear phase error 有权
标题翻译：用于检测线性相位误差的方法和装置
公开(公告)号：US07643599B2
公开(公告)日：2010-01-05
申请号：US11371320
申请日：2006-03-07
申请人： Andre Willis
发明人： Andre Willis
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03D13/003
摘要： Disclosed herein is a method and apparatus used to detect phase error information between edges of an input data signal and a clock signal for use at ultra-high frequencies and where linear phase error information is required. This invention extends the usefulness of a given integrated circuit logic technology to twice the frequency range of application while maintaining the desired linear phase error measurement operation. Flip flops are used to sample the data input signal with the clocking signal and processing is done separately for rising and falling data edges. Analog recombination of phase error information from both edges is then done in a fashion that is not limited by the integrated circuit speed. This invention overcomes limitations of prior methods in that it operates in data applications, provides linear phase error information at very high phase-error bandwidth and can operate at the same maximum speed as the flip flop and logic process technology will allow by operating on bit cells that are a full 1-bit minimum rather than half-bit cells.
摘要翻译：这里公开了一种用于检测输入数据信号的边缘与时钟信号之间的相位误差信息的方法和装置，其用于超高频并且需要线性相位误差信息。本发明将给定的集成电路逻辑技术的有用性扩展到应用的频率范围的两倍，同时保持期望的线性相位误差测量操作。触发器用于使用时钟信号对数据输入信号进行采样，并对数据上升沿和下降沿单独进行处理。然后以不受集成电路速度限制的方式对来自两个边缘的相位误差信息进行模拟复合。本发明克服了现有方法的局限性，因为它在数据应用中运行，提供非常高的相位误差带宽的线性相位误差信息，并且可以以与触发器和逻辑处理技术相同的最大速度工作，通过对位单元进行操作这是一个完整的1位最小值而不是半位单元。

6. 发明授权

US07466787B1 Multi-stage phase detector 有权
标题翻译：多级相位检测器
公开(公告)号：US07466787B1
公开(公告)日：2008-12-16
申请号：US10994053
申请日：2004-11-19
申请人： James P. Ross
发明人： James P. Ross
IPC分类号： H03D3/24
CPC分类号： H03D13/003 , H03L7/091 , H04L7/033
摘要： A multi-stage phase detector (four stages in one described embodiment) comprises a plurality of data paths and phase paths that are buffered from a received serial data input stream to reduce loading. Each data path recovers a data bit and further functions as a transition detector to detect consecutive data bits having similar logic states. An exclusive NOR gate in the data path produces a control signal to disable a multiplexer in the phase path when two data bits have similar logic states. Each phase path produces a sample of a serial data input stream and produces the sample to a multiplexer for coupling to a transconductance module. The multiplexer output is coupled to or decoupled from the transconductance module by the control signal from the data path to maintain phase-lock.
摘要翻译：多级相位检测器（一个描述的实施例中的四个级）包括从接收的串行数据输入流缓冲的多个数据路径和相位路径，以减少负载。每个数据路径恢复数据位并进一步起到转换检测器的作用，以检测具有相似逻辑状态的连续数据位。当两个数据位具有类似的逻辑状态时，数据通路中的异或非门产生一个控制信号，以禁止相位路径中的多路复用器。每个相位路径产生串行数据输入流的采样，并将采样产生到多路复用器以耦合到跨导模块。多路复用器输出通过来自数据路径的控制信号耦合到跨导模块或从跨导模块解耦，以保持相位锁定。

7. 发明授权

US07436921B1 Frequency sampling phase detector 有权
标题翻译：频率采样相位检测器
公开(公告)号：US07436921B1
公开(公告)日：2008-10-14
申请号：US10982968
申请日：2004-11-05
申请人： Mark M. Mulbrook , Robert A. Newgard
发明人： Mark M. Mulbrook , Robert A. Newgard
IPC分类号： H03D3/24 , H04L7/00
CPC分类号： H04L7/033 , H03D13/003 , H04L7/0087
摘要： The present invention is an apparatus for determining the phase difference between a reference frequency signal and an input signal. The frequency sampling phase detector of the present invention may include a phase detector coupled with sample and hold circuitry. The frequency sampling phase detector of the present invention may reduce the frequency of an input signal suitable for proportional and linear phase detection by the phase detector. Advantageously, the frequency sampling phase detector of the present invention may reduce power consumption over conventional phase detectors in combination with frequency dividers.
摘要翻译：本发明是用于确定参考频率信号和输入信号之间的相位差的装置。本发明的频率采样相位检测器可以包括与采样和保持电路耦合的相位检测器。本发明的频率采样相位检测器可以降低适用于相位检测器的比例和线性相位检测的输入信号的频率。有利地，本发明的频率采样相位检测器可以与分频器相结合地降低传统相位检测器的功耗。

8. 发明授权

US07432751B2 High performance signal generation 有权
标题翻译：高性能信号发生
公开(公告)号：US07432751B2
公开(公告)日：2008-10-07
申请号：US11430663
申请日：2006-05-09
申请人： Xu Fang
发明人： Xu Fang
IPC分类号： H03L7/00 , H03B10/00
CPC分类号： H03L7/085 , G01R25/04 , G01R31/31709 , G01R31/31922 , H03D13/003 , H03L7/087 , H03L7/091 , H03L7/16
摘要： A high performance phase detector includes a local digital oscillator for generating a digital reference signal of programmable frequency and phase. The phase detector accumulates a difference in phase between the digital reference signal and a sampled input signal to produce a measure of phase error. The phase detector can be advantageously used in a frequency synthesizer to produce signals with low phase noise and accurate phase control. Synthesizers of this type can further be used to as building blocks in ATE systems and other electronic systems for generating low jitter clocks and waveforms.
摘要翻译：高性能相位检测器包括用于产生可编程频率和相位的数字参考信号的本地数字振荡器。相位检测器累积数字参考信号和采样输入信号之间的相位差，以产生相位误差的测量。相位检测器可以有利地用在频率合成器中以产生具有低相位噪声和精确相位控制的信号。这种类型的合成器可进一步用作ATE系统和其他用于产生低抖动时钟和波形的电子系统的构建块。

9. 发明申请

US20080061838A1 Differential-type high-speed phase detector 审中-公开
标题翻译：差分式高速相位检测器
公开(公告)号：US20080061838A1
公开(公告)日：2008-03-13
申请号：US11518452
申请日：2006-09-11
申请人： Jinn-Shyan Wang , Yi-Ming Wang
发明人： Jinn-Shyan Wang , Yi-Ming Wang
IPC分类号： H03D13/00
CPC分类号： H03D13/003
摘要： A differential-type high-speed phase detector is provided, and it includes a first DTHT module and a second DTHT module wherein these two DTHT modules are the same. The first DTHT module includes a first input for receiving a signal CK_ref, a second input for receiving a signal CK_fb, a first logic unit, a second logic unit, a third logic unit and an output. An imperceptible delay period difference is produced by the difference of the capacitance value between two capacitors to diminish the size of the dead zone of the phase detector in accordance with the prior art. As a result, the differential-type high-speed phase detector also keeps high speed and tri-state outputs such that the performance of the dead zone is enhanced.
摘要翻译：提供差分式高速相位检测器，它包括第一DTHT模块和第二DTHT模块，其中这两个DTHT模块相同。第一DTHT模块包括用于接收信号CK_ref的第一输入端，用于接收信号CK_fb的第二输入端，第一逻辑单元，第二逻辑单元，第三逻辑单元和输出端。根据现有技术，通过两个电容器之间的电容值的差异产生不可察觉的延迟周期差，以减小相位检测器的死区的尺寸。结果，差分型高速相位检测器也保持高速度和三态输出，从而提高死区的性能。

10. 发明申请

US20070223634A1 METHOD AND APPARATUS FOR HIGH RESOLUTION MEASUREMENT OF SIGNAL TIMING 失效
标题翻译：用于信号时序高分辨率测量的方法和装置
公开(公告)号：US20070223634A1
公开(公告)日：2007-09-27
申请号：US11277400
申请日：2006-03-24
申请人： Bassel Haddad , Jacob Finkelstein
发明人： Bassel Haddad , Jacob Finkelstein
IPC分类号： H04L7/00 , H03D3/24
CPC分类号： H03L7/091 , H03D13/003
摘要： A phase measurement system for measuring a phase difference between an input signal and a reference signal, comprises: a phase comparator having a first input receiving a first sample of the input signal and a second sample of the input signal and having a second input receiving a clock derived from the reference signal, the phase comparator having an output representing a time between a crossing of a first threshold by the clock and a predetermined time along an interval from the first sample to the second sample where the input signal crosses a second threshold on the interval; an interpolator coupled to the first input and having an output indicative of an interpolated time of the second-threshold-crossing on the interval in the input signal; and a phase calculator coupled to the phase comparator output and the interpolator output and which computes the phase difference by combining the phase comparator output and the interpolator output.
摘要翻译：一种用于测量输入信号和参考信号之间的相位差的相位测量系统，包括：相位比较器，具有接收所述输入信号的第一采样的第一输入端和所述输入信号的第二采样，并具有接收第从参考信号导出的时钟，相位比较器具有表示在第一阈值与时钟交叉之间的时间的输出和沿着从第一采样到第二采样的间隔的预定时间，其中输入信号跨越第二阈值间隔; 内插器，其耦合到所述第一输入端，并且具有指示所述输入信号中的间隔上的所述第二阈值交叉的内插时间的输出; 以及相位计算器，其耦合到相位比较器输出和内插器输出，并且通过组合相位比较器输出和内插器输出来计算相位差。

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