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1. 发明公开

US20230370313A1 METHODS AND APPARATUS FOR PHASE CHANGE DETECTION USING A RESONATOR 审中-公开
公开(公告)号：US20230370313A1
公开(公告)日：2023-11-16
申请号：US18226327
申请日：2023-07-26
申请人： RAYTHEON COMPANY
发明人： Gary M. Graceffo , Andrew Kowalevicz , Benjamin P. Dolgin
IPC分类号： H04L27/22 , H03H7/00 , H01P7/06 , H03D3/00 , H03D3/26 , H04L27/233
CPC分类号： H04L27/22 , H01P7/06 , H03D3/00 , H03D3/006 , H03D3/26 , H03H7/00 , H04L27/2334
摘要： Disclosed is a microwave cavity resonator used as a phase change (phase modulation) to intensity change (intensity or amplitude modulation) converter. Certain aspects and embodiments include resonant circuits, such as a resistor, inductor and capacitor (RLC) circuit. Certain aspects and embodiments convert changes in phase to changes in output voltage to perform analog demodulation of a phase modulated microwave carrier. Certain aspects and embodiments use resonance when the reactive components of the circuit (capacitive and inductive components) are equal in magnitude and 180 degrees out of phase with one another, thereby cancelling out the reactance component of the circuit’s impedance.

2. 发明授权

US09143087B2 Adaptive FM demodulator supporting multiple modes 有权
标题翻译：自适应FM解调器支持多种模式
公开(公告)号：US09143087B2
公开(公告)日：2015-09-22
申请号：US14083900
申请日：2013-11-19
申请人： QUALCOMM Incorporated
发明人： Eunmo Kang , Le Nguyen Luong , Yossef Tsfaty
IPC分类号： H03D3/00 , H04L27/14 , H04L27/148 , H04L27/152 , H04B1/16
CPC分类号： H03D3/006 , H03D3/00 , H03D3/001 , H03D2200/0045 , H03D2200/0054 , H04B1/1646 , H04L27/14 , H04L27/148 , H04L27/152
摘要： Methods, systems, and devices are described for an adaptive demodulator that supports multiple modes. An FM signal may be received at a demodulator and parameters corresponding to the FM signal may be identified. Connections between multiple modules within the demodulator may be configured, based at least in part on the parameters, to select one of multiple demodulation modes supported by the demodulator to demodulate the FM signal. The modes may include a phase differencing mode, a phase-locked loop (PLL) mode, a frequency-compressive feedback (FCF) mode, and/or a quadrature detector mode. The parameters may include one or both of a signal strength of the FM signal and a maximum frequency deviation of the FM signal. Based on the parameters, one or more signals may be generated to configure the connections within the demodulator. A switch from one mode to another may occur when one of the parameters breaches a threshold value.
摘要翻译：为支持多种模式的自适应解调器描述了方法，系统和设备。可以在解调器处接收FM信号，并且可以识别与FM信号对应的参数。至少部分地基于参数，解调器内的多个模块之间的连接可以被配置为选择由解调器支持的多个解调模式之一以解调FM信号。这些模式可以包括相位差分模式，锁相环（PLL）模式，频率 - 压缩反馈（FCF）模式和/或正交检测器模式。参数可以包括FM信号的信号强度和FM信号的最大频率偏差中的一个或两个。基于这些参数，可以生成一个或多个信号来配置解调器内的连接。当其中一个参数违反阈值时，可能会发生从一种模式切换到另一种模式的切换。

3. 发明授权

US08873606B2 Transceiver including a high latency communication channel and a low latency communication channel 有权
标题翻译：收发器包括高延迟通信信道和低延迟通信信道
公开(公告)号：US08873606B2
公开(公告)日：2014-10-28
申请号：US13671340
申请日：2012-11-07
申请人： Broadcom Corporation
发明人： Heng Zhang , Mehdi Khanpour , Jun Cao , Chang Liu , Afshin Momtaz
IPC分类号： H04B1/38 , H03D3/02
CPC分类号： H04B1/745 , H03D3/006 , H03D3/02 , H04L7/033
摘要： Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.
摘要翻译：描述了减少收发器中的延迟的方法，系统和装置。收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。当在低延迟应用中使用收发器时，可以利用低延迟通信信道。通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。当低延迟通信信道用于传递数据时，实现数据速率的增加。可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。

4. 发明授权

US08841964B2 Apparatus and method for demodulating an input signal 有权
标题翻译：用于解调输入信号的装置和方法
公开(公告)号：US08841964B2
公开(公告)日：2014-09-23
申请号：US13578421
申请日：2010-03-10
申请人： Sadik Hafizovic , Flavio Heer , Stefan Koch , Niels Haandbaek
发明人： Sadik Hafizovic , Flavio Heer , Stefan Koch , Niels Haandbaek
IPC分类号： H03D3/04 , H03D1/22 , H03D3/00
CPC分类号： H03D3/006 , H03D1/22
摘要： An apparatus for demodulating an input signal that includes a frequency detector for tracking a frequency of the input signal, an oscillator and a mixer is disclosed. The input signal and an output signal of the oscillator can constitute the incoming signals for the mixer and the output signal of the mixer can constitute the demodulated input signal, wherein an arithmetic unit is arranged downstream of the frequency detector and upstream of the oscillator, wherein the tracked frequency of the input signal and a predefined second frequency constitute the incoming signals of the arithmetic unit and the arithmetic unit is designed such that it computes a control signal for the oscillator from the tracked frequency of the input signal and the predefined second frequency with the output signal of the oscillator depending on the control signal.
摘要翻译：公开了一种用于解调包括用于跟踪输入信号的频率的频率检测器的输入信号的装置，振荡器和混频器。振荡器的输入信号和输出信号可以构成混频器的输入信号，并且混频器的输出信号可以构成解调输入信号，其中算术单元布置在频率检测器的下游和振荡器的上游，其中输入信号的跟踪频率和预定的第二频率构成运算单元的输入信号，并且算术单元被设计成使得其根据输入信号的跟踪频率和预定义的第二频率来计算振荡器的控制信号，振荡器的输出信号取决于控制信号。

5. 发明申请

US20120313697A1 APPARATUS AND METHOD FOR DEMODULATING AN INPUT SIGNAL 有权
标题翻译：用于解调输入信号的装置和方法
公开(公告)号：US20120313697A1
公开(公告)日：2012-12-13
申请号：US13578421
申请日：2010-03-10
申请人： Sadik Hafizovic , Flavio Heer , Stefan Koch , Niels Haandbaek
发明人： Sadik Hafizovic , Flavio Heer , Stefan Koch , Niels Haandbaek
IPC分类号： H03D3/06
CPC分类号： H03D3/006 , H03D1/22
摘要： The invention relates to an apparatus (300; 400; 500; 600) for demodulating an input signal (306; 402; 520), comprising a frequency detector (302; 403; 502.1, . . . , 502. N; 603) for tracking a frequency (f2; fd1, . . . , fdN) of the input signal (306; 402; 520), an oscillator (304; 410; 505; 605, 606) and a mixer (305; 408; 507; 608, 609), wherein the input signal (306; 402; 520) and an output signal (307; 409) of the oscillator (304; 410; 505; 605, 606) constitute the incoming signals for the mixer (305; 408; 507; 608, 609) and the output signal of the mixer (305; 408; 507; 608, 609) constitutes the demodulated input signal, wherein an arithmetic unit (303; 404; 504; 604) is arranged downstream of the frequency detector (302; 403; 502.1, . . . , 502. N; 603) and upstream of the oscillator (304; 410; 505; 605, 606), wherein the tracked frequency (f2; fd1, . . . , fdN) of the input signal (306; 402; 520) and a predefined second frequency (f1; faux1, . . . , fauxM) constitute the incoming signals of the arithmetic unit (303; 404; 504; 604) and the arithmetic unit (303; 404; 504; 604) is designed such that it computes a control signal (f3; f4; fo1, . . . , foP) for the oscillator (304; 410; 505; 605, 606) from the tracked frequency (f2; fd1, . . . , fdN) of the input signal (306; 402; 520) and the predefined second frequency (f1; faux1, . . . , fauxM) with the output signal (307; 409) of the oscillator (304; 410; 505; 605, 606) depending on the control signal (f3; f4; fo1, . . . , foP). The invention furthermore relates to a method for demodulating an input signal (306; 402; 520) with such an apparatus (300; 400; 500; 600).
摘要翻译：本发明涉及一种用于解调输入信号（306; 402; 520）的装置（300; 400; 500; 600），包括频率检测器（302; 403; 502.1，...，502 N; 603）跟踪输入信号（306; 402; 520）的频率（f2; fd1，...，fdN），振荡器（304; 410; 505; 605,606）和混频器（305; 408; 507; 608 ，其中所述振荡器（304; 410; 505; 605,606）的所述输入信号（306; 402; 520）和输出信号（307; 409）构成所述混频器（305; 408; 507; 608,609），并且所述混频器（305; 408; 507; 608,609）的输出信号构成所述解调输入信号，其中运算单元（303; 404; 504; 604）被布置在所述频率检测器（302; 403; 502.1，...，502 N; 603）和振荡器（304; 410; 505; 605,606）的上游，其中，跟踪的频率（f2; fd1，...，fdN）输入信号（306; 402; 520）和预定义的第二频率（f1; faux1，...，fauxM）构成收入运算单元（303; 404; 504; 604）和算术单元（303; 404; 504; 604）被设计成使得它为振荡器（304; 410; 505; 605,606）计算控制信号（f3; f4; fo1，...，foP））与输出信号（306; 402; 520）的跟踪频率（f2; fd1，...，fdN）和预定义的第二频率（f1; faux1，...，fauxM）取决于控制信号（f3; f4; fo1，...，foP）的振荡器（304; 410; 505; 605，606）本发明还涉及一种用这种装置（300; 400; 500; 600）解调输入信号（306; 402; 520）的方法。

6. 发明授权

US08301103B2 Receiver with improved flicker noise performance 有权
标题翻译：接收机具有改善的闪烁噪声性能
公开(公告)号：US08301103B2
公开(公告)日：2012-10-30
申请号：US12879071
申请日：2010-09-10
申请人： Xiongchuan Huang , Guido Dolmans
发明人： Xiongchuan Huang , Guido Dolmans
IPC分类号： H04B1/10 , H04B1/16
CPC分类号： H03D3/006 , H03D1/22 , H03D2200/006 , H03F1/223 , H03F1/56
摘要： A method for demodulating an RF input signal using an envelope detector and synchronous switching of the input signal before entering and after leaving the envelope detector, the envelope detector having a non-linear transfer function acting essentially as a squaring function.The invention also relates to an electronic receiver circuit performing such a method, and to an RF receiver comprising such an electronic receiver, and to an electronic device comprising such an RF receiver, and to the use of such an RF receiver as a wake-up receiver.
摘要翻译：一种使用包络检波器解调RF输入信号并在输入和离开包络检测器之后对输入信号进行同步切换的方法，包络检测器具有基本上作为平方函数起作用的非线性传递函数。本发明还涉及一种执行这种方法的电子接收机电路，以及包括这种电子接收机的RF接收机以及包括这种RF接收机的电子设备，以及使用这样的RF接收机作为唤醒接收器。

7. 发明申请

US20120243643A1 APPARATUS AND METHOD OF DIFFERENTIAL IQ FREQUENCY UP-CONVERSION 失效
标题翻译：差分IQ频率上变换的装置和方法
公开(公告)号：US20120243643A1
公开(公告)日：2012-09-27
申请号：US13231244
申请日：2011-09-13
申请人： David F. SORRELLS , Michael J. Bultman , Robert W. Cook , Richad C. Looke , Charley D. Moses, JR. , Gregory S. Rawlins , Michael W. Rawlins
发明人： David F. SORRELLS , Michael J. Bultman , Robert W. Cook , Richad C. Looke , Charley D. Moses, JR. , Gregory S. Rawlins , Michael W. Rawlins
IPC分类号： H04L27/06
CPC分类号： H04B1/04 , H03C3/40 , H03D3/006 , H03D7/00 , H04B1/408 , H04B2001/0491 , H04L25/03
摘要： A balanced transmitter up-converts I and Q baseband signals directly from baseband-to-RF. The up-conversion process is sufficiently linear that no IF processing is required, even in communications applications that have stringent requirements on spectral growth. In operation, the balanced modulator sub-harmonically samples the I and Q baseband signals in a balanced and differential manner, resulting in harmonically rich signal. The harmonically rich signal contains multiple harmonic images that repeat at multiples of the sampling frequency, where each harmonic contains necessary information to reconstruct the I and Q baseband signals. The differential sampling is performed according to control signals that are phase shifted with respect to each other. The control signals may have pulse widths (or apertures) that operate to improve energy transfer to a desired harmonic in the harmonically rich signal. A bandpass filter can then be utilized to select the desired harmonic of interest from the harmonically rich signal.
摘要翻译：平衡发射机直接从基带到RF RF转换I和Q基带信号。上转换过程是足够的线性，即使在对频谱增长有严格要求的通信应用中也不需要IF处理。在运行中，平衡调制器以平衡和差分的方式对I和Q基带信号进行子谐波采样，从而产生谐波丰富的信号。谐波丰富的信号包含以抽样频率的倍数重复的多个谐波图像，其中每个谐波包含重建I和Q基带信号的必要信息。根据相对于彼此相移的控制信号进行差分采样。控制信号可以具有脉冲宽度（或孔径），其操作以改善在谐波丰富信号中的期望谐波的能量传递。然后可以利用带通滤波器从谐波丰富的信号中选择所需要的谐波。

8. 发明申请

US20120082280A1 SAMPLER CIRCUIT 有权
标题翻译：采样电路
公开(公告)号：US20120082280A1
公开(公告)日：2012-04-05
申请号：US13198401
申请日：2011-08-04
申请人： Paul Mateman , Johannes Petrus Antonius Frambach
发明人： Paul Mateman , Johannes Petrus Antonius Frambach
IPC分类号： H04L7/02
CPC分类号： H03L7/091 , H03D3/006 , H03L2207/50
摘要： A sampler circuit comprises a plurality of series-connected sampler cells and a detector circuit. Each successive stage comprises twice the number of sampler cells, in parallel, as the previous stage, and is clocked at half the sampling frequency of the previous stage. Each sampler cell comprises two parallel branches of series-connected clocked inverters. A clocked inverter is operative to invert an applied signal during one phase of an applied sampling clock, and to render a high impedance output during the other sampling clock phase. Successive clocked inverters are clocked with opposite (i.e., positive/negative) versions of the sampling clock. The detector circuit examines the outputs of the last stage of sampler cells, and may for example comprise an OR function to detect a state transition in an applied input signal. The sampler circuit exhibits immunity to metastability and low power consumption.
摘要翻译：采样器电路包括多个串联连接的采样器单元和检测器电路。每个连续级包括采样器单元的数量的两倍，并行地作为前一级，并且以前一级的采样频率的一半被计时。每个采样器单元包括串联连接的时钟反相器的两个并联分支。时钟反相器用于在施加的采样时钟的一个相位期间反转施加的信号，并且在另一采样时钟相位期间呈现高阻抗输出。连续的时钟反相器以采样时钟的相反（即正/负）版本计时。检测器电路检查采样器单元的最后级的输出，并且可以例如包括用于检测所施加的输入信号中的状态转换的OR功能。采样器电路具有亚稳态和低功耗的抗扰性。

9. 发明授权

US08149970B2 Multiple input, multiple output channel, digital receiver tuner 有权
标题翻译：多输入，多输出通道，数字接收机调谐器
公开(公告)号：US08149970B2
公开(公告)日：2012-04-03
申请号：US12491640
申请日：2009-06-25
申请人： Fabien Buda
发明人： Fabien Buda
IPC分类号： H04B1/10
CPC分类号： H04N21/4263 , H03D3/006 , H03D3/007 , H04B1/0003 , H04B1/406 , H04N5/4401 , H04N5/50 , H04N7/17309 , H04N21/4383
摘要： The present invention teaches a compact and highly integrated multiple-channel digital tuner and receiver architecture, suitable for widespread field deployment, wherein each receiver demodulator channel may be remotely, automatically, dynamically, and economically configured for a particular cable, carrier frequency, and signaling baud-rate, from an option universe that includes a plurality of input cables, a plurality of carrier frequencies, and a plurality of available baud-rates. A multiple coax input, multiple channel output, digital tuner is partitioned into a multiple coax input digitizer portion and a multiple channel output front-end portion. The digitizer portion consists of N digitizers and accepts input signals from N coax cables and digitizes them with respective A/D converters. The front-end portion consists of M front-ends and provides M channel outputs suitable for subsequent processing by M respective digital demodulators. In a first clock domain, a fixed predetermined A/D sampling rate is chosen to provide oversampling of the inputs by a common integer multiple of all the symbol rates of interest. A plurality other clock domains operate at selectable sub-multiples of the first domain as required to deliver a constant number of symbol samples at the output of each front-end. At the input to each of the M front-ends is a respective input selector coupled to each of the N streams of digitized input data followed by a digital signal scaler that dynamically scales the selected incoming stream of digitized input data as a function of the signal power of the channel's associated carrier.
摘要翻译：本发明教导了一种紧凑且高度集成的多通道数字调谐器和接收器架构，适用于广泛的现场部署，其中每个接收机解调器信道可以对于特定的电缆，载波频率和信号进行远程，自动，动态和经济地配置波特率，包括多个输入电缆，多个载波频率和多个可用波特率的选项范围。多个同轴电缆输入，多通道输出，数字调谐器被分割成多个同轴电缆输入数字转换器部分和多通道输出前端部分。数字转换器部分由N个数字转换器组成，并接受来自N个同轴电缆的输入信号，并将其与相应的A / D转换器进行数字化。前端部分由M个前端组成，并提供适合M个相应数字解调器后续处理的M通道输出。在第一时钟域中，选择固定的预定A / D采样率以通过所有符号利率的公共整数倍提供输入的过采样。多个其他时钟域在第一域的可选子倍数下操作，以便在每个前端的输出处递送恒定数量的符号样本。在M个前端中的每一个的输入端是相应的输入选择器，其耦合到数字化输入数据的N个流中的每一个，随后是数字信号缩放器，其根据信号动态地缩放所选择的数字化输入数据的输入流频道相关运营商的功率。

10. 发明授权

US08077797B2 Method, system, and apparatus for balanced frequency up-conversion of a baseband signal 有权
标题翻译：用于基带信号的平衡上变频的方法，系统和装置
公开(公告)号：US08077797B2
公开(公告)日：2011-12-13
申请号：US12823055
申请日：2010-06-24
申请人： David F. Sorrells , Michael J. Bultman , Robert W. Cook , Richard C. Looke , Charley D. Moses, Jr. , Gregory S. Rawlins , Michael W. Rawlins
发明人： David F. Sorrells , Michael J. Bultman , Robert W. Cook , Richard C. Looke , Charley D. Moses, Jr. , Gregory S. Rawlins , Michael W. Rawlins
IPC分类号： H04L27/04 , H04L27/12 , H04L27/20
CPC分类号： H04B1/0475 , H03C3/40 , H03D3/006 , H03D7/00 , H04L25/03
摘要： A balanced transmitter up-converts a baseband signal directly from baseband-to-RF. The up-conversion process is sufficiently linear that no IF processing is required, even in communications applications that have stringent requirements on spectral growth. In operation, the balanced modulator sub-harmonically samples the baseband signal in a balanced and differential manner, resulting in harmonically rich signal. The harmonically rich signal contains multiple harmonic images that repeat at multiples of the sampling frequency, where each harmonic contains the necessary information to reconstruct the baseband signal. The differential sampling is performed according to a first and second control signals that are phase shifted with respect to each other. In embodiments of the invention, the control signals have pulse widths (or apertures) that operate to improve energy transfer to a desired harmonic in the harmonically rich signal. A bandpass filter can then be utilized to select the desired harmonic of interest from the harmonically rich signal. The sampling modules that perform the sampling can be configured in either a series or a shunt configuration. In embodiments of the invention, DC offset voltages are minimized between the sampling modules to minimize or prevent carrier insertion into the harmonic images.
摘要翻译：平衡发射机直接从基带到RF RF转换基带信号。上转换过程是足够的线性，即使在对频谱增长有严格要求的通信应用中也不需要IF处理。在运行中，平衡调制器以平衡和差分的方式对基带信号进行子谐波采样，从而产生谐波丰富的信号。谐波丰富的信号包含以抽样频率的倍数重复的多个谐波图像，其中每个谐波包含必要的信息以重构基带信号。根据相对于彼此相移的第一和第二控制信号执行差分采样。在本发明的实施例中，控制信号具有脉冲宽度（或孔径），其操作以改善在谐波丰富信号中的期望谐波的能量传递。然后可以利用带通滤波器从谐波丰富的信号中选择所需要的谐波。执行采样的采样模块可以以串联或分流配置进行配置。在本发明的实施例中，采样模块之间的DC偏移电压最小化，以最小化或防止载波插入到谐波图像中。

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