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1. 发明申请

US20090096519A1 CONFIGURABLE DEMODULATOR AND DEMODULATION METHOD 有权
标题翻译：可配置的解调器和解调方法
公开(公告)号：US20090096519A1
公开(公告)日：2009-04-16
申请号：US12028292
申请日：2008-02-08
申请人： ALAA EL-AGHA , DUSTIN GRIESDORF , GARETH P. WEALE , JAKOB NIELSON
发明人： ALAA EL-AGHA , DUSTIN GRIESDORF , GARETH P. WEALE , JAKOB NIELSON
IPC分类号： H03D3/04
CPC分类号： H04L27/10 , H03D3/006 , H04L27/156 , H04L27/1563
摘要： A method and system for a frequency shift key demodulation is provided. The system includes a counting block for counting a reference clock within a window defined by a modulated signal, a detector for comparing a count value output from the counting block with digital multi-level thresholds and outputting baseband data based on the comparison, and a configurations block for configuring at least one of the counting block and the detector. The method includes counting a reference clock within a window defined by the FSK modulated signal and outputting a count value as a result of the counting, and comparing the count value with multi-level thresholds to output baseband data based on the comparison.
摘要翻译：提供了一种用于频移键解调的方法和系统。该系统包括用于对由调制信号定义的窗口内的参考时钟进行计数的计数块，用于将来自计数块的计数值与数字多电平阈值进行比较的检测器，以及基于比较输出基带数据的配置用于配置计数块和检测器中的至少一个的块。该方法包括对由FSK调制信号定义的窗口内的参考时钟进行计数，并作为计数结果输出计数值，并根据比较将计数值与多电平阈值进行比较以输出基带数据。

2. 发明授权

US5903187A Monolithically integrable frequency demodulator device 失效
标题翻译：单片可积分频率解调器
公开(公告)号：US5903187A
公开(公告)日：1999-05-11
申请号：US777044
申请日：1996-12-30
申请人： Claude Claverie , Xavier Guitton
发明人： Claude Claverie , Xavier Guitton
IPC分类号： H03D3/04 , H03D3/14 , H03K9/06
CPC分类号： H03K9/06 , H03D3/14
摘要： Frequency modulated signals are demodulated through a limiter circuit that chops the signal to give pulses whose occurrence frequency is proportional to the instant frequency of the received signal. The invention is devoted to a new processing of those pulses. The leading edges of the pulses are time integrated. The obtained signal is then as usual, low pass filtered to give the demodulated signal. The main advantage of this new processing is that the circuit that makes this processing does not implement delay lines and can then be made as a single chips.
摘要翻译：频率调制信号通过限幅器电路进行解调，该限幅器电路将信号切断，产生出现频率与接收信号的即时频率成比例的脉冲。本发明致力于对这些脉冲的新的处理。脉冲的前沿是时间积分的。所获得的信号是通常的，低通滤波以给出解调信号。这种新处理的主要优点是使得该处理的电路不实现延迟线，然后可以作为单个芯片。

3. 发明授权

US5708378A Frequency-to-voltage converting apparatus 失效
标题翻译：频率 - 电压转换装置
公开(公告)号：US5708378A
公开(公告)日：1998-01-13
申请号：US455895
申请日：1995-05-31
申请人： Masakiyo Horie , Takuya Harada
发明人： Masakiyo Horie , Takuya Harada
IPC分类号： G01P3/481 , G01P3/48 , G01P3/489 , G01R23/06 , G01R23/15 , H03D3/04 , H03K9/06
CPC分类号： G01P3/4805 , H03K9/06 , G01R23/06 , H03D3/04
摘要： In a frequency-to-voltage converting circuit, a clamping frequency is maintained constant without being adversely influenced by circuit constants, and temperature characteristics. The frequency-to-voltage converting apparatus has voltage converting means for converting a frequency of an input pulse signal into a voltage, arranged by frequency judging means for judging whether or not the frequency of the input pulse signal reaches a predetermined clamping frequency. Setting pulse signal generating means outputs a setting pulse signal having the clamping frequency, and means for causing the voltage converting means to convert the frequency of the input pulse signal into the voltage when the frequency of the input pulse signal does not reach the clamping frequency based on a judgement result of the frequency judging means. The voltage converting means is caused to convert the clamping frequency of the setting pulse signal derived from the setting pulse signal generating means when the frequency of the input pulse signal reaches the clamping frequency.
摘要翻译：在频率 - 电压转换电路中，钳位频率保持恒定，而不受电路常数和温度特性的不利影响。频率 - 电压转换装置具有电压转换装置，用于将输入脉冲信号的频率转换为电压，由频率判断装置设置，用于判断输入脉冲信号的频率是否达到预定的钳位频率。设置脉冲信号发生装置输出具有钳位频率的设置脉冲信号，以及用于当输入脉冲信号的频率未达到钳位频率时使电压转换装置将输入脉冲信号的频率转换为电压的装置关于频率判断装置的判断结果。当输入脉冲信号的频率达到钳位频率时，电压转换装置转换从设置脉冲信号产生装置导出的设置脉冲信号的钳位频率。

4. 发明授权

US4959620A Frequency demodulation circuit 失效
标题翻译：频率解调电路
公开(公告)号：US4959620A
公开(公告)日：1990-09-25
申请号：US408220
申请日：1989-09-18
申请人： Masahiro Honjo
发明人： Masahiro Honjo
IPC分类号： G11B20/06 , H03D3/00 , H03D3/04 , H04N5/92 , H04N5/931
CPC分类号： H03D3/04 , H04N5/92 , H04N5/9315
摘要： A frequency demodulation circuit disclosed superposes pulses on an input frequency-modulated (FM) signal at substantially peaks of the FM signal before demodulating the FM signal so that zero cross points of the FM signal can be correctly restored. A peak detection circuit detects peaks of the FM signal or peaks of the fundamental wave of the FM signal, which substantially correspond to the peaks of the FM signal. A pulse generating circuit generates, from the peak detection result, a train of pulses respectively occurring at the same timings as those of the detected peak occurrance timings. The generated train of pulses and the FM signal are respectively fed to differential inputs of a differential input type limiter. An output signal of the limiter is fed to a pulse count circuit to obtain a frequency demodulated signal.

5. 发明授权

US4800338A Pulse count type FM demodulator 失效
标题翻译：脉冲计数型FM解调器
公开(公告)号：US4800338A
公开(公告)日：1989-01-24
申请号：US67179
申请日：1987-06-29
申请人： Shigeo Yoshizawa , Eiichi Ishii
发明人： Shigeo Yoshizawa , Eiichi Ishii
IPC分类号： H03D3/00 , H03D3/04 , H03K9/06 , H03K17/66
CPC分类号： H03K17/667 , H03D3/04 , H03K9/06
摘要： An FM demodulator having improved demodulation sensitivity, and suitable for monolithic integration. As demonstrated in various embodiments, increased sensitivity is made possible= by narrowing the demodulation band on a low frequency side. According to the various embodiments, a monostable multivibrator or first pulse generator receives an input signal and provides an output having first and second states having a combined duration equal to one period of the input signal, or alternatively equal to one-half period of the input signal. A second pulse generator, responsive to the output of the first pulse generator, generates another output having third and fourth states whose combined duration is the same as the combined duration of the first and second states. Demodulation is accomplished finally through a low-pass filter, which integrates the output of the second pulse generator.
摘要翻译： FM解调器具有改进的解调灵敏度，适用于单片集成。如在各种实施例中所证明的，通过使低频侧的解调频带变窄，可以提高灵敏度。根据各种实施例，单稳态多谐振荡器或第一脉冲发生器接收输入信号并提供具有等于输入信号的一个周期的组合持续时间的第一和第二状态的输出，或者等于输入的一半周期信号。响应于第一脉冲发生器的输出的第二脉冲发生器产生具有第三和第四状态的另一输出，其组合持续时间与第一和第二状态的组合持续时间相同。最终通过低通滤波器完成解调，该低通滤波器对第二脉冲发生器的输出进行积分。

6. 发明授权

US4785255A Digital FSK signal demodulator 失效
标题翻译：数字FSK信号解调器
公开(公告)号：US4785255A
公开(公告)日：1988-11-15
申请号：US124154
申请日：1987-11-23
申请人： Mark Lucak , Michael Klein
发明人： Mark Lucak , Michael Klein
IPC分类号： H04L27/156 , H04L27/233 , H03D3/04
CPC分类号： H04L27/2335 , H04L27/1566
摘要： A demodulator for a phase coherent frequency shift keyed signal has a master clock which generates a signal having a plurality of pulses during each half of the bit internal of the FSK signal. A detector determines during which master clock pulse within several groups of X number of pulses the most transitions occur in the received signal. Based on the determined clock pulse, samples taken in each of two consecutive half-bit intervals of the FSK signal are selected for comparison to produce the demodulator output signal.
摘要翻译：用于相位相移频移键控信号的解调器具有主时钟，该主时钟在FSK信号内部的位的每一半期间产生具有多个脉冲的信号。检测器确定在几组X个脉冲之间的哪个主时钟脉冲在接收信号中发生大多数转换。基于确定的时钟脉冲，选择FSK信号的两个连续半位间隔中的每一个采样，以进行比较以产生解调器输出信号。

7. 发明授权

US4489430A FM Stereo demodulation circuit 失效
标题翻译： FM立体声解调电路
公开(公告)号：US4489430A
公开(公告)日：1984-12-18
申请号：US408993
申请日：1982-08-17
申请人： Kohji Ishida , Tatsuo Numata , Tadashi Noguchi
发明人： Kohji Ishida , Tatsuo Numata , Tadashi Noguchi
IPC分类号： H03D1/22 , H03D3/04 , H04H1/00 , H04H40/45 , H04H40/72 , H04H5/00
CPC分类号： H04H40/72 , H03D1/2227 , H03D3/04
摘要： A pulse position modulated (PPM) signal is derived from an input FM signal, and first and second switching signals are derived which are opposite in phase and correspond to alternating half cycles of the PPM signal. First and second opposite phase subcarrier signals are derived synchronized to the pilot signal in the input FM signal, and various combinations of the switching and subcarrier signals are multiplied together and the multiplication products combined to obtain left and right channel outputs.
摘要翻译：从输入FM信号导出脉冲位置调制（PPM）信号，导出与相位相反并对应于PPM信号的交替半周期的第一和第二切换信号。导出与输入FM信号中的导频信号同步的第一和第二相反相位副载波信号，并将切换和副载波信号的各种组合相乘在一起，乘积合成以获得左右声道输出。

8. 发明授权

US4350957A Pulse counter-type FM detector 失效
标题翻译：脉冲计数式FM检测器
公开(公告)号：US4350957A
公开(公告)日：1982-09-21
申请号：US140821
申请日：1980-04-16
申请人： Yukihiko Miyamoto
发明人： Yukihiko Miyamoto
IPC分类号： H03D3/00 , H03K3/033 , H03K9/06 , H03D3/04 , H03K3/284 , H04B1/16
CPC分类号： H03K3/033 , H03K9/06
摘要： In a pulse counter-type FM detector circuit for obtaining audio signals at an output terminal by detecting FM signals in the following order through a limiter circuit, a trigger pulse generating circuit, a monostable circuit and an integrator connected to the output terminal where the monostable circuit comprises a gate circuit having at least two inputs where trigger pulses from the trigger pulse generating circuit are applied to a first one of the two inputs and a feedback signal to the other input, a differentiating circuit responsive to the output from the gate circuit, a differential inverter having a power supply and where the integrator includes an LC type low pass filter connected to the output side of the differential inverter circuit, the improvement comprising a terminal resistor connected between the power supply and the output terminal so that a part of the current flowing in the differential inverter circuit is diverted through the terminal resistor.
摘要翻译：在脉冲计数式FM检测器电路中，通过限幅电路检测FM信号，通过检测FM信号，触发脉冲发生电路，单稳态电路和积分器，连接到输出端，其中单稳态电路包括具有至少两个输入的门电路，其中来自触发脉冲发生电路的触发脉冲被施加到两个输入中的第一个输入端，反馈信号被施加到另一输入端，响应于来自门电路的输出的微分电路，具有电源的差分逆变器，并且积分器包括连接到差分逆变器电路的输出侧的LC型低通滤波器，其改进包括连接在电源和输出端子之间的端子电阻，使得一部分在差分逆变器电路中流动的电流通过端子电阻转向。

9. 发明授权

US4122405A Digital logic level signal indication of phase and frequency lock condition in a phase-locked loop 失效
标题翻译：锁相环中相位和频率锁定状态的数字逻辑电平信号指示
公开(公告)号：US4122405A
公开(公告)日：1978-10-24
申请号：US844409
申请日：1977-10-21
申请人： Gary William Tietz , Keith James Mueller
发明人： Gary William Tietz , Keith James Mueller
IPC分类号： H03K5/26 , H03L7/089 , H03L7/095 , H03D3/04 , H03K5/20
CPC分类号： H03K5/26 , H03L7/095 , H03L7/089 , Y10S331/02
摘要： A digital logic level signal indicates whether a first signal in a phase-locked loop is locked in phase and frequency with a second signal provided to the loop. The digital logic level signal is provided from the sequentially last stage of a counter having a predetermined number of stages. The counter counts cycles in an input signal corresponding to one of the first signal and the second signal. A reset signal pulse having a first predetermined duration is provided to the counter from a pulse width discriminator when the pulse width discriminator detects a phase difference between the first and second signals of greater than a second predetermined duration. The reset signal pulse resets the counter. The digital logic level signal is in a state indicating an in-lock condition when a predetermined number of input signal cycles occur without the counter being reset.
摘要翻译：数字逻辑电平信号指示锁相环中的第一信号是否以提供给环路的第二信号锁相在相位和频率上。从具有预定级数的计数器的顺序最后一级提供数字逻辑电平信号。计数器对与第一信号和第二信号之一相对应的输入信号中的周期进行计数。当脉冲宽度鉴别器检测到第一和第二信号之间的相位差大于第二预定持续时间时，具有第一预定持续时间的复位信号脉冲从脉冲宽度鉴别器提供给计数器。复位信号脉冲复位计数器。当预定数量的输入信号周期发生而计数器不被复位时，数字逻辑电平信号处于指示锁定状态的状态。

10. 发明授权

US3997893A Synchro digitizer 失效
标题翻译：同步数字化仪
公开(公告)号：US3997893A
公开(公告)日：1976-12-14
申请号：US270351
申请日：1972-07-10
申请人： John E. Games , Henry E. Martin , Kirk S. Walworth
发明人： John E. Games , Henry E. Martin , Kirk S. Walworth
IPC分类号： H03M1/64 , H03K13/02 , H03D3/04
CPC分类号： H03M1/645
摘要： The differences between two pairs of the three windings of a synchro stator are individually scaled so as to provide a function of the rotor angle plus a 45.degree. phase lead. The scaled values are applied to a CR/RC bridge, the output of which bears a phase relationship relating directly to the synchro rotor angle, but is identical for shaft angles from 0.degree. to 180.degree. and from 180.degree. to 360.degree.. These signals are shaped and applied to a pulsewidth modulator; the pulsewidth modulation ambiguity is resolved by generation of a sign bit indicative of angles between 180.degree. and 360.degree.. The pulsewidth modulated output is converted to an analog level, as is the reference supply voltage, and an analog to digital converter provides a digital output as a function of the ratio of the angle voltage level to the reference voltage level. The sign bit is provided as an additional digital bit thereby providing a digital output indication of shaft angle. Multiplexing of synchro inputs to the apparatus may be provided if desired.
摘要翻译：同步定子的三对绕组的两对之间的差异被单独缩放，以提供转子角加45度相位的功能。缩放值应用于CR / RC桥，其输出与直接与同步转子角相关的相位关系，但对于0°至180°和180°至360°的轴角度相同。这些信号被成形并施加到脉宽调制器; 通过产生指示180°和360°之间的角度的符号位来解决脉宽调制模糊度。脉冲宽度调制输出与参考电源电压一样转换为模拟电平，模数转换器提供数字输出作为角度电压电平与参考电压电平的比值的函数。符号位被提供为附加数字位，从而提供轴角度的数字输出指示。如果需要，可以提供同步输入到设备的多路复用。

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