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    • 6. 发明授权
    • Amplifier compression adjustment circuit
    • 放大器压缩调节电路
    • US08013674B2
    • 2011-09-06
    • US12853951
    • 2010-08-10
    • Serge Francois DrogiVikas Vinayak
    • Serge Francois DrogiVikas Vinayak
    • H03G3/20
    • H03F3/24H03F1/0227H03F1/0238H03F1/0266H03F1/0272H03F1/3247H03F3/195H03F2200/105H03F2200/408H03F2200/78H03F2200/99
    • An RF power amplifier system adjusts the supply voltage to the power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the RF input signal and an attenuated amplitude of the RF output signal of the power amplifier. A variable gain amplifier (VGA) adjusts the amplitude of the RF input signal, thus providing a second means of adjusting the amplitude of the output of the power amplifier. The gain of the VGA or the supply voltage to the power amplifier is controlled based on the AC components of the amplitude correction signal, while the DC components of the amplitude correction signal are blocked from controlling the VGA or the supply voltage to the power amplifier. The DC level of the gain control of the VGA, the average supply voltage to the power amplifier, or the closed loop gain of the overall amplitude correction loop is controlled separately by a compression control signal.
    • RF功率放大器系统基于指示RF输入信号的幅度与功率放大器的RF输出信号的衰减幅度之间的幅度差的幅度校正信号来调整功率放大器的电源电压。 可变增益放大器(VGA)调整RF输入信号的幅度,从而提供调整功率放大器的输出幅度的第二装置。 基于幅度校正信号的AC分量来控制VGA的增益或功率放大器的电源电压,同时阻止幅度校正信号的直流分量控制VGA或向功率放大器供电。 VGA的增益控制的直流电平,功率放大器的平均电源电压或整个幅度校正环路的闭环增益由压缩控制信号分别控制。
    • 7. 发明授权
    • DCDC converter unit, power amplifier, and base station using the same
    • DCDC转换器单元,功率放大器以及使用其的基站
    • US07957710B2
    • 2011-06-07
    • US12216092
    • 2008-06-30
    • Takashi KawamotoTakashi OshimaTaizo YamawakiManabu Nakamura
    • Takashi KawamotoTakashi OshimaTaizo YamawakiManabu Nakamura
    • H04B1/04H04M1/00
    • H03F1/0227H03F1/0205H03F1/32H03F3/24H03F2200/102H03F2200/99
    • A DCDC converter includes a signal splitting unit that splits an input signal into N signal components; N DCDC converter elements that process individually the N split signals; and an adder that adds outputs from the plural DCDC converter elements to generate output signals. Each of the DCDC converter elements has an operation band narrower than an applicable frequency band of the input signal, and selects a design parameter that allows a conversion efficiency of the DCDC converter elements to be optimized for any band of the applicable frequency bands. For example, the parameter of a PMOS transistor and a NMOS transistor, which configure an inverter is designed to optimize the efficiency at any of frequency bands. The frequency band of the input signal is split, and each of the split outputs is input to a DCDC converter element that has a corresponding frequency and high efficiency characteristic.
    • DCDC转换器包括将输入信号分解为N个信号分量的信号分离单元; N个DCDC转换器元件,分别处理N个分离信号; 以及加法器,其添加来自多个DCDC转换器元件的输出以产生输出信号。 每个DCDC转换器元件具有比输入信号的适用频带窄的操作频带,并且选择允许DCDC转换器元件的转换效率针对适用频带的任何频带进行优化的设计参数。 例如,配置反相器的PMOS晶体管和NMOS晶体管的参数被设计为优化任何频带处的效率。 输入信号的频带被分离,并且每个分离输出被输入到具有对应的频率和高效率特性的DCDC转换器元件。