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1. 发明授权

US10381993B1 Single controller automatic calibrating circuits for reducing or canceling offset voltages in operational amplifiers in an instrumentation amplifier 有权
公开(公告)号：US10381993B1
公开(公告)日：2019-08-13
申请号：US16045103
申请日：2018-07-25
申请人： QUALCOMM Incorporated
发明人： Burt Lee Price , Jin Liang , Yeshwant Nagaraj Kolla
IPC分类号： H03F3/45 , H03F1/02
CPC分类号： H03F3/45995 , H03F1/02 , H03F3/45977 , H03F2200/375
摘要： Single controller automatic calibrating circuits for reducing or canceling offset voltages in operational amplifiers (op-amps) in an instrumentation amplifier are disclosed. An automatic calibrating op-amp system is provided that includes an instrumentation amplifier, which includes a front-end amplifier circuit comprising at least one front-end op-amp and a final-stage amplifier circuit comprising a final-stage op-amp. The op-amp(s) can include auxiliary differential inputs for offset voltage cancellation. The automatic calibrating op-amp system also includes an automatic calibration circuit employing a single controller to generate calibration signals on a calibration output to an auxiliary differential input(s) of an op-amp(s) in the instrumentation amplifier for offset voltage cancellation. The automatic calibration circuit includes a single controller to generate calibration signals to the instrumentation amplifier to reduce or cancel offset voltage, thereby eliminating the need to provide multiple automatic calibration circuits or an automatic calibration circuit employing multiple controllers.

2. 发明授权

US09966915B2 Programmable amplifier and method of operating the same 有权
公开(公告)号：US09966915B2
公开(公告)日：2018-05-08
申请号：US15222355
申请日：2016-07-28
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Abdullah Ahmed , Frederick Edward Sykes
IPC分类号： H03F1/34 , H03G3/30 , H03F3/45
CPC分类号： H03G3/30 , H03F3/45475 , H03F3/45995 , H03F2200/171 , H03F2203/45044 , H03G1/0088 , H03G1/0094 , H03G3/001 , H03G5/28
摘要： A programmable amplifier includes an amplifier, an input capacitor, a feedback circuit, and a high-pass filter circuit. The amplifier has an input coupled to the input capacitor for receiving an input signal. The feedback circuit includes multiple feedback capacitors of differing capacitance values that are each selectively coupled between the output of the amplifier and the input of the amplifier using multiple first switches. The high-pass filter circuit includes multiple switched capacitors of differing capacitance values that are each selectively coupled between the amplifier output and a ground node using multiple second switches. The first switches are configured to be selectively switched on for activating at least one feedback capacitor to adjust a gain of the amplifier, while the second switches are configured to be selectively switched at a first and second phase of a clock signal to adjust a high-pass cutoff frequency of the amplifier independently of how the gain is adjusted.

3. 发明申请

US20180034430A1 PROGRAMMABLE AMPLIFIER AND METHOD OF OPERATING THE SAME 有权
公开(公告)号：US20180034430A1
公开(公告)日：2018-02-01
申请号：US15222355
申请日：2016-07-28
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Abdullah AHMED , Frederick Edward SYKES
IPC分类号： H03G3/30 , H03F3/45
CPC分类号： H03G3/30 , H03F3/45475 , H03F3/45995 , H03F2200/171 , H03F2203/45044 , H03G1/0088 , H03G1/0094 , H03G3/001 , H03G5/28
摘要： A programmable amplifier includes an amplifier, an input capacitor, a feedback circuit, and a high-pass filter circuit. The amplifier has an input coupled to the input capacitor for receiving an input signal. The feedback circuit includes multiple feedback capacitors of differing capacitance values that are each selectively coupled between the output of the amplifier and the input of the amplifier using multiple first switches. The high-pass filter circuit includes multiple switched capacitors of differing capacitance values that are each selectively coupled between the amplifier output and a ground node using multiple second switches. The first switches are configured to be selectively switched on for activating at least one feedback capacitor to adjust a gain of the amplifier, while the second switches are configured to be selectively switched at a first and second phase of a clock signal to adjust a high-pass cutoff frequency of the amplifier independently of how the gain is adjusted.

4. 发明申请

US20150236661A1 AMPLIFICATION CIRCUIT, AMPLIFICATION DEVICE, AFE CIRCUIT, AND SIGNAL PROCESSING SYSTEM 有权
标题翻译：放大电路，放大器件，AFE电路和信号处理系统
公开(公告)号：US20150236661A1
公开(公告)日：2015-08-20
申请号：US14471194
申请日：2014-08-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shigeo IMAI , Shinji NAKATSUKA
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F3/45977 , H03F3/45995 , H03F2203/45116 , H03F2203/45171 , H03F2203/45522 , H03F2203/45591
摘要： According to one embodiment, an amplification circuit includes first and second differential amplification circuits, each having an output connected to an output terminal and a feedback resistor connected between the output and a negative input of the respective differential amplification circuit. The amplification circuit includes a switching circuit that receives a first signal on first input terminal and a second signal on a second input terminal and includes set of switches that is configured to apply the first and second signals to the first and second differential amplification circuits such that in a first switching state an amplified voltage difference of the first and second signals is available between the two output terminals, and in a second switching state an amplified current difference of the first and second signals is available between the two output terminals.
摘要翻译：根据一个实施例，放大电路包括第一和第二差分放大电路，每个具有连接到输出端的输出端和连接在相应的差分放大电路的输出端和负输入端之间的反馈电阻器。放大电路包括开关电路，其接收第一输入端子上的第一信号和第二输入端子上的第二信号，并且包括被配置为将第一和第二信号施加到第一和第二差分放大电路的开关组，使得在第一开关状态下，第一和第二信号的放大电压差在两个输出端之间可用，而在第二开关状态下，第一和第二信号的放大的电流差在两个输出端之间是可用的。

5. 发明申请

US20150214911A1 Circuitry And Methods For Common-Mode Rejection Calibration 有权
标题翻译：共模抑制校准的电路和方法
公开(公告)号：US20150214911A1
公开(公告)日：2015-07-30
申请号：US14166370
申请日：2014-01-28
申请人： Silicon Laboratories Inc.
发明人： Michael S. Johnson , Russell Croman
IPC分类号： H03F3/45 , H03F1/56
CPC分类号： H03F1/56 , H03F3/45941 , H03F3/45977 , H03F3/45995 , H03F2203/45048 , H03F2203/45078 , H03F2203/45082 , H03F2203/45171 , H03F2203/45522 , H03F2203/45538 , H03F2203/45576 , H03F2203/45591 , H03F2203/45616
摘要： Circuitry and methods are disclosed that may employ common mode calibration circuitry configured to at least partially calibrate out impedance differences or mismatches between the differential signal paths of differential signal circuitry. The common mode calibration circuitry may be integrated as an internal part of integrated differential signal circuitry that includes a differential amplifier to reject common mode noise, and may be used to reduce or substantially eliminate any external and/or internal difference in signal path resistance that exists between the differential signal paths of the integrated differential signal circuitry. A common mode calibration signal may be internally or externally applied to the signal inputs of differential signal circuitry, and used to determine a setting for the common mode calibration circuitry that at least partially calibrates out impedance differences or mismatches between the differential signal paths of differential signal circuitry.
摘要翻译：公开了可以采用共模校准电路的电路和方法，其配置为至少部分地校准差分信号电路的差分信号路径之间的阻抗差或失配。共模校准电路可以集成为集成差分信号电路的内部部分，其包括用于抑制共模噪声的差分放大器，并且可以用于减少或基本消除存在的信号路径电阻中的任何外部和/或内部差异在集成差分信号电路的差分信号路径之间。共模校准信号可以在内部或外部施加到差分信号电路的信号输入端，并且用于确定共模校准电路的设置，其至少部分地校准差分信号的差分信号路径之间的阻抗差或失配电路。

6. 发明申请

US20150091630A1 RF POWER DETECTOR AND DETECTION METHOD 有权
标题翻译：射频功率检测器和检测方法
公开(公告)号：US20150091630A1
公开(公告)日：2015-04-02
申请号：US14478780
申请日：2014-09-05
申请人： NXP B.V.
发明人： Lucie Chandernagor , Patrick Jean
IPC分类号： H03K5/003
CPC分类号： H03K5/003 , H03F3/19 , H03F3/45995 , H04B10/6933
摘要： The invention provides an RF detection circuit and method using an envelope detector having an output connected to a first input of a differential amplifier and a reference storage capacitor to a second input of the differential amplifier. In a preferred implementation of the calibration mode, there is initial discharging of a reference storage capacitor, high speed charging of the reference storage capacitor until the differential amplifier output toggles, then slower discharging of the reference storage capacitor until the differential amplifier output toggles again. The resulting voltage is stored on the reference storage capacitor for use in a subsequent detection mode. This provides storage of an offset voltage which calibrates both the envelope detector differential amplifier functions.
摘要翻译：本发明提供了一种使用包络检测器的RF检测电路和方法，该包络检测器具有连接到差分放大器的第一输入端的输出端和对差分放大器的第二输入端的参考存储电容器。在校准模式的优选实施方式中，存在参考存储电容器的初始放电，参考存储电容器的高速充电直到差分放大器输出切换，然后慢速放电参考存储电容器直到差分放大器输出再次切换。所得到的电压存储在参考存储电容器上，用于随后的检测模式。这提供了对包络检测器差分放大器功能进行校准的偏移电压的存储。

7. 发明申请

US20140028286A1 AMPLIFIER CIRCUITS AND METHODS 有权
标题翻译：放大器电路和方法
公开(公告)号：US20140028286A1
公开(公告)日：2014-01-30
申请号：US13711571
申请日：2012-12-11
申请人： Jinxi Hu , Jiabin Wang , Xujiang Huang
发明人： Jinxi Hu , Jiabin Wang , Xujiang Huang
IPC分类号： G01R15/20
CPC分类号： G01R15/202 , G01R33/07 , H03F3/387 , H03F3/45475 , H03F3/45995 , H03F2200/261 , H03F2203/45138 , H03F2203/45528 , H03F2203/45538 , H03F2203/45551 , H03F2203/45588 , H03F2203/45624 , H03F2203/45634 , H03F2203/45681
摘要： A chopper amplifier circuit for sensing Hall voltage with reduced offsets includes a Hall sampling circuit with a first switching circuit for selectively coupling each of four nodes of a Hall plate to either a power source or a ground terminal. The circuit also includes a differential amplifier and a second switching circuit configured for selectively coupling each of the four nodes to inputs of the differential amplifier. A Hall voltage signal retaining circuit includes two groups of four storage devices and a second group of four storage devices. A third switching circuit is configured for outputs of the differential amplifier to selected ones of the storage devices. A fourth switching circuit is configured for selectively coupling the storage devices outputs of the chopper amplifier circuit.
摘要翻译：用于以减小的偏移量检测霍尔电压的斩波放大器电路包括具有第一开关电路的霍尔采样电路，用于选择性地将霍尔板的四个节点中的每一个耦合到电源或接地端子。电路还包括差分放大器和配置用于选择性地将四个节点中的每一个耦合到差分放大器的输入的第二开关电路。霍尔电压信号保持电路包括两组四个存储装置和第二组四个存储装置。第三开关电路被配置用于将差分放大器的输出与所选存储器件的输出相配合。第四开关电路被配置为选择性地耦合斩波放大器电路的存储设备输出。

8. 发明授权

US06833759B2 System and method for a programmable gain amplifier 有权
标题翻译：可编程增益放大器的系统和方法
公开(公告)号：US06833759B2
公开(公告)日：2004-12-21
申请号：US10208042
申请日：2002-07-31
申请人： David A. Sobel
发明人： David A. Sobel
IPC分类号： H03G330
CPC分类号： H03G1/0088 , H03F3/45192 , H03F3/4539 , H03F3/45739 , H03F3/45995 , H03F2203/45521 , H03F2203/45594 , H03F2203/45601 , H03F2203/45616 , H03F2203/45698 , H03F2203/45726
摘要： Provided is system for an improved programmable gain amplifier (PGA). The system includes an amplifier and a first gain control mechanism. The first gain control mechanism includes a circuit input port and is positioned along a feedback path of the amplifier. The first gain control mechanism is configured to (i) receive an input signal and (ii) moderate gains applied to the received input signal, the applied gains including gain values of greater than or equal to one. A second gain control mechanism is coupled to the first gain control mechanism and is integrated with a function of the amplifier. The second gain control mechanism (i) provides gain values of less than one and (ii) decreases a feedback factor of the amplifier when the gain values are provided having values of less than one.
摘要翻译：提供了一种用于改进的可编程增益放大器（PGA）的系统。该系统包括放大器和第一增益控制机构。第一增益控制机构包括电路输入端口并且沿着放大器的反馈路径定位。第一增益控制机制被配置为（i）接收输入信号和（ii）适用于所接收的输入信号的中等增益，所施加的增益包括大于或等于1的增益值。第二增益控制机构耦合到第一增益控制机构并与放大器的功能集成。第二增益控制机构（i）提供小于1的增益值，并且当提供具有小于1的增益值时，减小放大器的反馈因数。

9. 发明授权

US06756924B2 Circuit and method for DC offset calibration and signal processing apparatus using the same 失效
标题翻译：用于直流偏移校准的电路和方法及使用其的信号处理装置
公开(公告)号：US06756924B2
公开(公告)日：2004-06-29
申请号：US10438941
申请日：2003-05-16
申请人： Junghwan Lee , Bo-Eun Kim , Jinkyu Lim , Minsu Jeong , Bonkee Kim
发明人： Junghwan Lee , Bo-Eun Kim , Jinkyu Lim , Minsu Jeong , Bonkee Kim
IPC分类号： H03M110
CPC分类号： H03F3/45995 , H03F2200/294 , H03F2200/372
摘要： A signal processing apparatus for correcting DC offset in a communication system is provided. The signal processing apparatus comprises: a low noise amplifier (LNA) 301; a mixer 303 for mixing the output from said LNA 301 with local oscillation signal LO; a first offset correction amplifier 305 for amplifying output signal from said mixer 303 and for eliminating DC offset in the output signal in accordance with first control signal Vc31; a second offset correction amplifier 309 for amplifying output signal from said first offset correction amplifier 305 and for eliminating DC offset in the output signal in accordance with second control signal Vc32; a variable gain amplifier 311 for amplifying output from said second offset correction amplifier 309 wherein gain is controlled such that power level of output be maintained to a desired value; offset calibration mean 313 for calibrating DC offset in output from said variable gain amplifier 311; and offset correction mean 315 for outputting the first and second control signals Vc31 and Vc32 in accordance with the output from said offset calibration mean 313, to eliminate DC offset in the output from said variable gain amplifier 311.
摘要翻译：提供一种用于校正通信系统中的DC偏移的信号处理装置。信号处理装置包括：低噪声放大器（LNA）301; 用于将来自所述LNA 301的输出与本地振荡信号LO混频的混频器303; 用于放大来自所述混频器303的输出信号并根据第一控制信号Vc31消除输出信号中的DC偏移的第一偏移校正放大器305; 第二偏移校正放大器309，用于放大来自所述第一偏移校正放大器305的输出信号，并根据第二控制信号Vc32消除输出信号中的DC偏移; 用于放大来自所述第二偏移校正放大器309的输出的可变增益放大器311，其中增益被控制使得输出的功率电平保持到期望值; 用于校准来自所述可变增益放大器311的输出中的直流偏移的偏移校准平均值313; 以及偏移校正平均值315，用于根据所述偏移校准平均值313的输出输出第一和第二控制信号Vc31和Vc32，以消除所述可变增益放大器311的输出中的DC偏移。

10. 发明申请

US20030155974A1 METHOD AND CIRCUIT FOR TRIMMING OFFSET AND TEMPERATURE DRIFT FOR OPERATIONAL AMPLIFIERS AND VOLTAGE REFERENCES 有权
标题翻译：用于操作放大器和电压参考的偏移和温度变化的方法和电路
公开(公告)号：US20030155974A1
公开(公告)日：2003-08-21
申请号：US10079977
申请日：2002-02-19
发明人： Vadim V. Ivanov , Junlin Zhou , Wally Meinel
IPC分类号： H03F003/45
CPC分类号： H03F3/45995 , H03F1/303 , H03F3/45771 , H03F2200/261
摘要： A trimming circuit and method of trimming is provided for offset and temperature drift trimming of an op amp or voltage reference device, having an input stage, on at least two different temperatures. The trimming circuit has a current source stage, having first and second current sources which are trimmed at a first temperature, in a first step, to balance the currents of the first and second current sources. The two current sources are configured to be selectively connected, in a second step and at the first temperature, to the offset-control terminal(s) of the input stage and thereby to trim the output of the input stage. The first and second current sources also have different temperature coefficients and are interchangeable with other current sources to facilitate changing, in a third step, the temperature coefficient of one of the two current sources to facilitate offset trimming at a second temperature.
摘要翻译：提供微调电路和修整方法用于在至少两个不同温度下具有输入级的运算放大器或参考电压装置的偏移和温度漂移微调。微调电路具有电流源级，具有在第一步骤中被修整在第一温度的第一和第二电流源，以平衡第一和第二电流源的电流。两个电流源被配置为在第二步骤和第一温度下选择性地连接到输入级的偏移控制端子，从而修整输入级的输出。第一和第二电流源还具有不同的温度系数，并且可与其它电流源互换，以便于在第三步骤中改变两个电流源之一的温度系数，以便于在第二温度下进行偏移修整。

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