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1. 发明授权

US10536143B1 Comparator architecture and related methods 有权
公开(公告)号：US10536143B1
公开(公告)日：2020-01-14
申请号：US16570173
申请日：2019-09-13
申请人： QUALCOMM Incorporated
发明人： Burt Lee Price , Dhaval Shah
IPC分类号： H03K17/22 , G06F1/24 , G01R19/165
摘要： A system is disclosed. The system includes a first stage configured to receive VIN and VREF, the first stage including an input transistor pair, wherein the input voltage is coupled to the input transistor pair, the input transistor pair is coupled to ground, and the input transistor pair includes at a common drain a high-gain node having a voltage VHGN. The system further include a second stage coupled to the high-gain node and configured to generate VOUT based on a difference between VIN and VREF, the second stage comprising a resistor and an inverter transistor pair, wherein the gates of the inverter transistor pair are coupled to the high-gain node of the first stage and the resistor couples the high-gain node of first stage to a common drain of the inverter transistor pair and is configured to provide and/or draw current to and/or from the high-gain node of first stage.

2. 发明申请

US20170344102A1 ADAPTIVE VOLTAGE MODULATION CIRCUITS FOR ADJUSTING SUPPLY VOLTAGE TO REDUCE SUPPLY VOLTAGE DROOPS AND MINIMIZE POWER CONSUMPTION 审中-公开
公开(公告)号：US20170344102A1
公开(公告)日：2017-11-30
申请号：US15604038
申请日：2017-05-24
申请人： QUALCOMM Incorporated
发明人： Yeshwant Nagaraj Kolla , Jeffrey Todd Bridges , Sanjay Patel , Shraddha Sridhar , Burt Lee Price , Gabriel Martel Tarr
IPC分类号： G06F1/32 , H02M1/08
CPC分类号： G06F1/3296 , G06F1/324 , G06F1/3287 , H02M1/08 , H02M3/157 , H02M2001/0025
摘要： Adaptive voltage modulation circuits for adjusting supply voltage to reduce supply voltage droops and minimize power consumption are provided. In one aspect, an adaptive voltage modulation circuit detects a supply voltage droop by detecting when a supply voltage falls below a droop threshold voltage, and adjusts a clock signal provided to a load circuit in response to a supply voltage droop. The adaptive voltage modulation circuit keeps a count of the number of clock signal cycles during which the supply voltage is below the droop threshold voltage. The adaptive voltage modulation circuit increases the supply voltage in response to the count exceeding an upper threshold value, and decreases the supply voltage in response to the count being less than a lower threshold value at an end of a defined period. The adaptive voltage modulation circuit can reduce the time a load circuit operates with reduced frequency while minimizing power consumption.

3. 发明授权

US09712126B2 Automatically calibrating operational amplifier (op-amp) systems for mitigating effects of offset voltages 有权
公开(公告)号：US09712126B2
公开(公告)日：2017-07-18
申请号：US15085122
申请日：2016-03-30
申请人： QUALCOMM Incorporated
发明人： Burt Lee Price , Yeshwant Nagaraj Kolla , Dhaval Rajeshbhai Shah , Ajay Janardanan
IPC分类号： H03F3/45
CPC分类号： H03F3/45071 , H03F3/45973 , H03F2200/153 , H03F2200/78 , H03F2203/45048
摘要： Automatically calibrating operational amplifier (op-amp) systems for mitigating effects of offset voltages are disclosed. In one aspect, an automatically calibrating op-amp system is provided that employs an analog calibration signal corresponding to a calibration mode to compensate an output voltage signal of an op-amp corresponding to an amplify mode. An automatic calibration circuit is included that employs a successive approximation register (SAR) controller configured to successively generate digital values based on the output voltage signal of the op-amp in response to a mode signal indicating the calibration mode. The automatic calibration circuit includes a digital-to-analog converter (DAC) configured to convert each successive digital value into the analog calibration signal in response to the mode signal indicating the calibration mode. The analog calibration signal is provided to an auxiliary differential input of the op-amp to compensate for the composite offset voltage in the amplify mode.

4. 发明申请

US20160070277A1 DISTRIBUTED VOLTAGE NETWORK CIRCUITS EMPLOYING VOLTAGE AVERAGING, AND RELATED SYSTEMS AND METHODS 有权
标题翻译：使用电压平均分布式电压网络电路及相关系统和方法
公开(公告)号：US20160070277A1
公开(公告)日：2016-03-10
申请号：US14482456
申请日：2014-09-10
申请人： QUALCOMM Incorporated
发明人： Burt Lee Price , Yeshwant Nagaraj Kolla , Dhaval Rajeshbhai Shah
IPC分类号： G05F1/46 , G01R19/00
CPC分类号： G05F1/46 , G01R19/003 , G01R31/3004 , H01L22/30
摘要： Distributed voltage network circuits employing voltage averaging, and related systems and methods are disclosed. In one aspect, because voltage in one area of a distributed load circuit may vary from voltage in a second area, a distributed voltage network circuit is configured to tap voltages from multiple areas to calculate average voltage in the distributed load circuit. The distributed voltage network circuit includes a voltage distribution source component having source nodes. Voltage is distributed from each source node to a corresponding voltage load node via resistive interconnects. Voltage tap nodes access voltage from each corresponding voltage load node. Each voltage tap node is coupled to an input node of a corresponding resistive element in voltage averaging circuit. An output node of each resistive element is coupled to a voltage output node of the voltage averaging circuit, generating the average voltage of the distributed load circuit on the voltage output node.
摘要翻译：公开了使用电压平均的分布式电压网络电路，以及相关的系统和方法。一方面，由于分布式负载电路的一个区域中的电压可以与第二区域中的电压变化，所以分布式电压网络电路被配置为从多个区域分接电压以计算分布式负载电路中的平均电压。分布式电压网络电路包括具有源节点的电压分配源组件。电压通过电阻互连从每个源节点分配到相应的电压负载节点。电压抽头节点访问每个相应的电压负载节点的电压。每个电压抽头节点耦合到电压平均电路中对应的电阻元件的输入节点。每个电阻元件的输出节点耦合到电压平均电路的电压输出节点，产生电压输出节点上的分布式负载电路的平均电压。

5. 发明授权

US10447292B1 Multiple-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuits 有权
公开(公告)号：US10447292B1
公开(公告)日：2019-10-15
申请号：US16113720
申请日：2018-08-27
申请人： QUALCOMM Incorporated
发明人： Burt Lee Price
IPC分类号： H03M1/12 , H03M1/14 , H03M7/16
摘要： Multiple-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuits are disclosed. In one aspect, a multiple-bit parallel SAR ADC circuit includes a number of SAR controller circuits, each of which includes SAR register circuits. Each SAR register circuit receives and stores a corresponding digital bit that is based on a comparison of an analog input signal and a corresponding digital-to-analog converter (DAC) analog signal. Each SAR register circuit also provides a corresponding digital signal based on the digital bit. A DAC circuit receives a reference voltage, and uses the reference voltage and a subset of digital signals generated by SAR controller circuits to generate multiple DAC analog signals. A compare circuit generates the digital bit corresponding to each SAR controller circuit, wherein a number of the digital bits are generated in parallel. Each digital bit collectively forms a digital representation of the analog input signal.

6. 发明授权

US10345834B2 Sensing total current of distributed load circuits independent of current distribution using distributed voltage averaging 有权
公开(公告)号：US10345834B2
公开(公告)日：2019-07-09
申请号：US15672356
申请日：2017-08-09
申请人： QUALCOMM Incorporated
发明人： Burt Lee Price , Yeshwant Nagaraj Kolla , Dhaval Rajeshbhai Shah , Jin Liang , Yu Sun , Hans Lee Yeager
IPC分类号： G01R19/28 , G05F1/565 , G01R19/00 , G01R19/10 , H02M1/00
摘要： Aspects for sensing total current of distributed load circuits independently of a spatial profile of the total current using distributed voltage averaging are disclosed. In one aspect, a current sense circuit is configured to sense total current of a distributed load circuit independently of where current is distributed. The current sense circuit includes distributed voltage averaging circuits configured to determine average voltages of the distributed load circuit based on voltages sensed at multiple resistive paths corresponding to a distribution network configured to provide voltage to the distributed load circuit. An amplifier includes an output node having an output voltage that is proportional to total current flowing in the distributed load circuit. The current sense circuit allows for sensing total current independent of where the current flows, providing more accurate current sensing compared to sensing current in one area of the distributed load circuit.

7. 发明授权

US10333544B1 Digital-to-analog converter (DAC) circuits employing resistor rotator circuits configured to be included in analog-to-digital converter (ADC) circuits 有权
公开(公告)号：US10333544B1
公开(公告)日：2019-06-25
申请号：US16135985
申请日：2018-09-19
申请人： QUALCOMM Incorporated
发明人： Burt Lee Price
IPC分类号： H03M1/12 , H03M1/46 , H03M1/78
摘要： Digital-to-analog converter (DAC) circuits employing resistor rotator circuits configured to be included in analog-to-digital converter (ADC) circuits are disclosed. In one aspect, a DAC circuit includes multiple DAC stages, each of which may be configured to generate one or more DAC analog signals corresponding to selected resistances within the DAC stage. Each DAC stage is configured to receive a corresponding top and bottom voltage. Each DAC stage is configured to generate a number of DAC analog signals based on the corresponding top voltage and the corresponding bottom voltage, as well as on the selected resistance of the DAC stage. Each DAC stage includes an adjusting circuit comprising a resistance configured to adjust a resistance of the corresponding DAC stage such that a parallel combination of the resistance of the adjusting circuit and a resistance of a next DAC stage is maintained at an ideal resistance level.

8. 发明授权

US09625924B2 Leakage current supply circuit for reducing low drop-out voltage regulator headroom 有权
公开(公告)号：US09625924B2
公开(公告)日：2017-04-18
申请号：US14860717
申请日：2015-09-22
申请人： QUALCOMM Incorporated
发明人： Francois Ibrahim Atallah , Hoan Huu Nguyen , Keith Alan Bowman , Yeshwant Nagaraj Kolla , Burt Lee Price , Samantak Gangopadhyay
IPC分类号： G05F1/56
CPC分类号： G05F1/56 , H03K19/0008
摘要： Systems and methods relate to a low-dropout voltage (LDO) voltage regulator which receives a maximum supply voltage and provides a regulated voltage to a load, where the load may be a processing core of a multi-core processing system. A leakage current supply source includes a leakage current sensor to determine a leakage current demand of the load of the LDO voltage regulator and a leakage current supply circuit to supply the leakage current demand. In this manner, the leakage current supply source provides current assistance to the LDO voltage regulator, such that the LDO voltage regulator can supply only dynamic current. Thus, headroom voltage of the LDO voltage regulator, which is a difference between the maximum supply voltage and the regulated voltage, can be reduced. Reducing the headroom voltage allows greater number of dynamic voltage and frequency scaling states of the load.

9. 发明申请

US20160308355A1 AUTOMATIC VOLTAGE SWITCHING CIRCUIT FOR SELECTING A HIGHER VOLTAGE OF MULTIPLE SUPPLY VOLTAGES TO PROVIDE AS AN OUTPUT VOLTAGE 有权
标题翻译：用于选择更高电压的多电源供应电压作为输出电压的自动电压开关电路
公开(公告)号：US20160308355A1
公开(公告)日：2016-10-20
申请号：US14862773
申请日：2015-09-23
申请人： QUALCOMM Incorporated
发明人： Burt Lee Price , Yeshwant Nagaraj Kolla , Neel Shashank Natekar
IPC分类号： H02J1/10
CPC分类号： H02J1/10 , H03K5/2481 , H03K19/0016 , H03K19/00315
摘要： Automatic voltage switching circuits for providing a higher voltage of multiple supply voltages are disclosed. In one aspect, an automatic voltage switching circuit is configured to generate a compare signal indicating which of a first supply voltage and a second supply voltage is a higher voltage. The automatic voltage switching circuit is further configured to generate first and second select signals based on the compare signal, wherein the first and second select signals are in a voltage domain of the higher voltage. Transistors corresponding to the first and second supply voltages control switching the output voltage to the higher voltage in response to the first and second select signals. Biasing the back-gates of the transistors using the output voltage reduces or avoids forward biasing in the body diodes of the transistors, thus reducing the possibility of the output voltage causing interference on a power supply corresponding to a non-activated transistor.
摘要翻译：公开了用于提供更高电压的多电源电压的自动电压开关电路。一方面，自动电压切换电路被配置为产生指示第一电源电压和第二电源电压中的哪一个是较高电压的比较信号。自动电压切换电路还被配置为基于比较信号产生第一和第二选择信号，其中第一和第二选择信号处于较高电压的电压域中。对应于第一和第二电源电压的晶体管响应于第一和第二选择信号控制将输出电压切换到较高电压。使用输出电压来偏置晶体管的背栅极减小或避免晶体管体二极管中的正向偏置，从而降低输出电压对与非激活晶体管相对应的电源产生干扰的可能性。

10. 发明授权

US10381993B1 Single controller automatic calibrating circuits for reducing or canceling offset voltages in operational amplifiers in an instrumentation amplifier 有权
公开(公告)号：US10381993B1
公开(公告)日：2019-08-13
申请号：US16045103
申请日：2018-07-25
申请人： QUALCOMM Incorporated
发明人： Burt Lee Price , Jin Liang , Yeshwant Nagaraj Kolla
IPC分类号： H03F3/45 , H03F1/02
CPC分类号： H03F3/45995 , H03F1/02 , H03F3/45977 , H03F2200/375
摘要： Single controller automatic calibrating circuits for reducing or canceling offset voltages in operational amplifiers (op-amps) in an instrumentation amplifier are disclosed. An automatic calibrating op-amp system is provided that includes an instrumentation amplifier, which includes a front-end amplifier circuit comprising at least one front-end op-amp and a final-stage amplifier circuit comprising a final-stage op-amp. The op-amp(s) can include auxiliary differential inputs for offset voltage cancellation. The automatic calibrating op-amp system also includes an automatic calibration circuit employing a single controller to generate calibration signals on a calibration output to an auxiliary differential input(s) of an op-amp(s) in the instrumentation amplifier for offset voltage cancellation. The automatic calibration circuit includes a single controller to generate calibration signals to the instrumentation amplifier to reduce or cancel offset voltage, thereby eliminating the need to provide multiple automatic calibration circuits or an automatic calibration circuit employing multiple controllers.

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