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    • 3. 发明申请
    • Digital Filter
    • 数字滤波器
    • US20120331026A1
    • 2012-12-27
    • US13591516
    • 2012-08-22
    • Andreas Menkhoff
    • Andreas Menkhoff
    • G06F17/10
    • H03H17/028H03H17/0433
    • A first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.
    • 数字滤波器的第一级接收要被滤波的输入数据,在第一时钟操作的数字滤波器的第一级; 数字滤波器的第二级输出滤波输出数据,数字滤波器的第二级在第二时钟上工作,其中第一时钟的频率与第二时钟的频率的比率是小数,频率 的第二时钟的频率高于第一时钟的频率; 第一级接收第一时钟和第二时钟的比率的指示; 并且第一级接收在(1)在第一时钟的第一时钟脉冲和第一时钟脉冲之间发生的第二时钟的时钟脉冲之间的时间偏移的指示,以及(2)第一时钟的第一时钟脉冲 第一时钟
    • 4. 发明授权
    • Digital filter
    • 数字滤波器
    • US08271568B2
    • 2012-09-18
    • US12201465
    • 2008-08-29
    • Andreas Menkhoff
    • Andreas Menkhoff
    • G06F17/17
    • H03H17/028H03H17/0433
    • Methods and apparatuses in which a first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.
    • 数字滤波器的第一级接收要滤波的输入数据,在第一时钟操作的数字滤波器的第一级的方法和装置; 数字滤波器的第二级输出滤波输出数据,数字滤波器的第二级在第二时钟上工作,其中第一时钟的频率与第二时钟的频率的比率是小数,频率 的第二时钟的频率高于第一时钟的频率; 第一级接收第一时钟和第二时钟的比率的指示; 并且第一级接收在(1)在第一时钟的第一时钟脉冲和第一时钟脉冲之间发生的第二时钟的时钟脉冲之间的时间偏移的指示,以及(2)第一时钟的第一时钟脉冲 第一时钟
    • 6. 发明申请
    • Device and method for polyphase resampling
    • 多相重采样的装置和方法
    • US20090261994A1
    • 2009-10-22
    • US11904328
    • 2007-09-26
    • Mihail Petrov
    • Mihail Petrov
    • H03M7/00
    • H03H17/0685H03H17/0275H03H17/028H03H17/0657H03H2218/06
    • The invention relates to a method and a device for polyphase resampling, having a coefficient generator (11) which provides a plurality of coefficients (C0, C1, . . . C5) and an interpolation arrangement used to carry out the resampling by means of the coefficients (C0-C5) applied to input data provided for resampling (Din; Yin, Uin, Vin) in order to provide output data (Dout; Yout, Uout, Vout). In this case it is preferred when the coefficient generator (11) is constructed and/or controlled so as to provide the coefficients (C0-C5) for the resampling in the form of linearly interpolated coefficients. It is in particular advantageous when a plurality of at least two data interpolation filters are provided for the interpolation of a corresponding number of parallel input data (Yin, Uin, Vin), wherein the coefficients (C0-C5) are input to each of the data interpolation filters.
    • 本发明涉及一种用于多相重采样的方法和装置,具有提供多个系数(C0,C1,...,C5)的系数发生器(11)和用于执行重采样的插值装置 为了提供输出数据(Dout; Yout,Uout,Vout),应用于提供给重采样(Din; Yin,Uin,Vin)的输入数据的系数(C0-C5)。 在这种情况下,当系数发生器(11)被构造和/或控制以便以线性内插系数的形式提供用于重采样的系数(C0-C5)时,是优选的。 当提供多个至少两个数据内插滤波器用于插入相应数量的并行输入数据(Yin,Uin,Vin)时,特别有利的是其中系数(C0-C5)被输入到 数据插值滤波器。
    • 9. 发明授权
    • Adaptive sampling rate converter
    • 自适应采样率转换器
    • US07369637B1
    • 2008-05-06
    • US10861937
    • 2004-06-04
    • Volker Mauer
    • Volker Mauer
    • H04L7/00H04L25/00H04L25/40
    • H03H17/0628H03H17/028H04L7/0029Y10S370/914
    • Apparatus, methods and techniques for adjusting the phase offset used in sampling rate conversion uses a Farrow structure or the like to compensate for clock problems such as “clock jitter” and/or “clock drift” effects, which typically arise where one clock is truly independent of the other. A phase offset adjustment value Δμ based on the measured data flow between clock domains across a transition interface and/or through a buffer is calculated. Where an output FIFO buffer is used, the measured data flow value represents the number of data words written to and read from the FIFO buffer, such as the current number of data words stored in the FIFO buffer or a counter value representing the net number of data words written to the FIFO buffer. The measured data flow value is compared to a target data flow value, which may be a range of values. The phase offset adjustment value may be updated and/or recalculated continuously and/or periodically and is added to or subtracted from the phase offset μ as necessary. Such systems are useful in software defined radio and the like and may be implemented on a variety of devices, including PLDs.
    • 用于调整采样率转换中使用的相位偏移的装置,方法和技术使用Farrow结构等来补偿时钟问题,例如“时钟抖动”和/或“时钟漂移”效应,这通常在一个时钟是真实的 独立于其他。 计算基于过渡接口和/或通过缓冲器的时钟域之间的测量数据流的相位偏移调整值Deltamu。 在使用输出FIFO缓冲器的情况下,测量的数据流量值表示写入FIFO缓冲器和从FIFO缓冲器读取的数据字的数量,例如存储在FIFO缓冲器中的当前数据字的数量或表示 数据字写入FIFO缓冲区。 将测量的数据流值与目标数据流值进行比较,其可以是值的范围。 相位偏移调整值可以根据需要连续地和/或周期性地更新和/或重新计算并被添加到或从相位偏移量mu中减去。 这样的系统在软件定义的无线电等中是有用的,并且可以在包括PLD的各种设备上实现。