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1. 发明授权

US09928870B1 System and method for providing an output signal without or with reduced jitter based upon an input signal notwithstanding phase changes in a clock signal 有权
公开(公告)号：US09928870B1
公开(公告)日：2018-03-27
申请号：US15720036
申请日：2017-09-29
申请人： NXP B.V.
发明人： Edwin Schapendonk
IPC分类号： H03M1/66 , G11B20/10 , H03M1/88 , G01R31/317
CPC分类号： G11B20/10268 , G01R31/31725 , G11B20/10037 , G11B20/10203 , G11B20/10222 , H03M1/0836 , H03M1/661 , H03M1/742 , H03M1/765 , H03M1/88
摘要： Systems and methods for providing an output signal based at least in part upon an input signal and a clock signal in a manner in which jitter is avoided or diminished, including for example a digital-to-analog converter (DAC), are disclosed herein. In one example embodiment, such a system includes an output signal generating component, a first component having a first switch and a variable characteristic, and a plurality of second components each having a respective additional switch and a respective fixed characteristic. A value of the variable characteristic is set at least in part based upon input and clock signals so that, when the variable characteristic influences at least indirectly the generating of the output signal by the output signal generating component, the output signal attains a first level that at least indirectly depends upon a phase of the clock signal relative to the input signal.

2. 发明授权

US09900017B1 Digital to analog conversion using semi-digital FIR filter 有权
公开(公告)号：US09900017B1
公开(公告)日：2018-02-20
申请号：US15485781
申请日：2017-04-12
申请人： Apple Inc.
发明人： Brian D. Clark
IPC分类号： H03M1/66 , H03M1/06 , H03K5/15 , H03H17/02 , H03F3/181
CPC分类号： H03M1/0626 , H03H15/00 , H03H17/06 , H03K5/15046 , H03M1/66 , H03M1/661 , H03M1/742
摘要： A semi-digital finite impulse response, FIR, filter is configured as a sparse FIR filter and as a minimum phase lag FIR filter. The FIR filter has a delay line composed of a number of sets of delay units sequentially coupled to each other, and where some of the sets of delay units have one or more untapped delay units as part of a cascade of two or more single-sample delay units. An analog summing node is coupled to the taps and produces at its output an analog version of a digital input signal that is fed to an input of the delay line. Other embodiments are also described and claimed.

3. 发明授权

US09728261B2 High performance digital to analog converter 有权
公开(公告)号：US09728261B2
公开(公告)日：2017-08-08
申请号：US15448813
申请日：2017-03-03
申请人： STMicroelectronics S.r.l.
发明人： Antonino Conte , Maria Giaquinta
IPC分类号： G11C16/04 , G11C16/06 , H03M1/66 , H03F3/45
CPC分类号： G11C16/06 , H03F1/34 , H03F3/347 , H03F3/45 , H03F3/45475 , H03F3/45977 , H03F2200/156 , H03F2200/375 , H03F2200/453 , H03F2203/45101 , H03F2203/45332 , H03F2203/45514 , H03F2203/45546 , H03F2203/45632 , H03M1/661
摘要： A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.

4. 发明申请

US20170178731A1 HIGH PERFORMANCE DIGITAL TO ANALOG CONVERTER 审中-公开
公开(公告)号：US20170178731A1
公开(公告)日：2017-06-22
申请号：US15448813
申请日：2017-03-03
申请人： STMicroelectronics S.r.l.
发明人： Antonino Conte , Maria Giaquinta
IPC分类号： G11C16/06 , H03F3/45 , H03M1/66
CPC分类号： G11C16/06 , H03F1/34 , H03F3/347 , H03F3/45 , H03F3/45475 , H03F3/45977 , H03F2200/156 , H03F2200/375 , H03F2200/453 , H03F2203/45101 , H03F2203/45332 , H03F2203/45514 , H03F2203/45546 , H03F2203/45632 , H03M1/661
摘要： A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.

5. 发明授权

US09640261B2 High performance digital to analog converter 有权
公开(公告)号：US09640261B2
公开(公告)日：2017-05-02
申请号：US15198161
申请日：2016-06-30
申请人： STMICROELECTRONICS S.R.L.
发明人： Antonino Conte , Maria Giaquinta
IPC分类号： G11C16/04 , G11C16/06 , H03F1/34 , H03F3/347 , H03F3/45 , H03M1/66
CPC分类号： G11C16/06 , H03F1/34 , H03F3/347 , H03F3/45 , H03F3/45475 , H03F3/45977 , H03F2200/156 , H03F2200/375 , H03F2200/453 , H03F2203/45101 , H03F2203/45332 , H03F2203/45514 , H03F2203/45546 , H03F2203/45632 , H03M1/661
摘要： A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.

6. 发明授权

US09559699B1 CMOS global interconnect using multi-voltage(or current)-levels 有权
标题翻译： CMOS全球互连使用多电压（或电流）级
公开(公告)号：US09559699B1
公开(公告)日：2017-01-31
申请号：US15004683
申请日：2016-01-22
申请人： ALTERA CORPORATION
发明人： Weimin Zhang , Yanzhong Xu
IPC分类号： H03K19/177 , H03K17/687 , H03M1/66 , H03K5/159
CPC分类号： H03K19/1774 , H03K5/159 , H03M1/661
摘要： A method and apparatus for reducing global interconnect delay on a field programmable gate array (FPGA) on an integrated circuit die comprising coding with a digital to analog coder on the integrated circuit die successive groups of n digital bits into an 2n level voltage or current signal where n is an integer greater than or equal to 2; transmitting the voltage or current signal on a global interconnect on the integrated circuit die; receiving on the integrated circuit die the signal transmitted on the global interconnect; and decoding the received signal on the integrated circuit die to reconstitute the successive groups of digital bits.
摘要翻译：一种用于减少集成电路管芯上的现场可编程门阵列（FPGA）上的全局互连延迟的方法和装置，其包括利用集成电路上的数模转换器对连续的n个数字位组进行编码为2n电平电压或电流信号其中n是大于或等于2的整数; 在集成电路管芯上的全局互连上传输电压或电流信号; 在集成电路上接收在全局互连上传输的信号; 以及对集成电路管芯上的接收信号进行解码以重构连续的数字位组。

7. 发明授权

US09484946B2 Digital-to-analog converter (DAC), method for operating a DAC and transceiver circuit 有权
标题翻译：数模转换器（DAC），用于操作DAC和收发器电路的方法
公开(公告)号：US09484946B2
公开(公告)日：2016-11-01
申请号：US14468078
申请日：2014-08-25
申请人： NXP B.V.
发明人： Mattieu Deloge , Arnoud Pieter van der Wel
IPC分类号： H04B1/38 , H03M1/66 , H03M1/08 , H03M1/74
CPC分类号： H03M1/661 , H03M1/0881 , H03M1/745 , H04B1/38
摘要： Embodiments of digital-to-analog converters (DACs), methods for operating a DAC, and transceiver circuits are described. In one embodiment, a DAC includes an input terminal configured to receive a digital signal, a converter circuit configured to convert the digital signal into an analog signal using first-order interpolation allowing low electromagnetic emissions, and an output terminal configured to output the analog signal. Other embodiments are also described.
摘要翻译：描述了数模转换器（DAC）的实施例，用于操作DAC的方法和收发器电路。在一个实施例中，DAC包括被配置为接收数字信号的输入端子，被配置为使用允许低电磁发射的一阶插值将数字信号转换成模拟信号的转换器电路，以及被配置为输出模拟信号的输出端子。还描述了其它实施例。

8. 发明申请

US20160314841A1 HIGH PERFORMANCE DIGITAL TO ANALOG CONVERTER 审中-公开
公开(公告)号：US20160314841A1
公开(公告)日：2016-10-27
申请号：US15198161
申请日：2016-06-30
申请人： STMICROELECTRONICS S.R.L.
发明人： Antonino CONTE , Maria GIAQUINTA
IPC分类号： G11C16/06 , H03F3/45 , H03M1/66
CPC分类号： G11C16/06 , H03F1/34 , H03F3/347 , H03F3/45 , H03F3/45475 , H03F3/45977 , H03F2200/156 , H03F2200/375 , H03F2200/453 , H03F2203/45101 , H03F2203/45332 , H03F2203/45514 , H03F2203/45546 , H03F2203/45632 , H03M1/661
摘要： A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.

9. 发明申请

US20160065233A1 Digital-to-Analog Converter 有权
标题翻译：数模转换器
公开(公告)号：US20160065233A1
公开(公告)日：2016-03-03
申请号：US14783321
申请日：2014-04-03
申请人： RENESAS ELECTRONICS EUROPE GMBH
发明人： Bushan Vohora
IPC分类号： H03M1/66 , H03M1/06
CPC分类号： H03M1/661 , H03M1/0626 , H03M1/668 , H03M1/82
摘要： A digital-to-analog converter (DAC) is described. The DAC comprises a resistor having a resistance R and a capacitor having a capacitance C. The DAC comprises a first switching element configured, in response to a first control signal, to couple the capacitor to a first rail via a path having a resistance less than R and a second switching element configured, in response to a second control signal, to couple the capacitor to the first rail through the resistor. The DAC also comprises a third switching element configured, in response to a third control signal, to couple the capacitor to a second rail (8) via a path having a resistance less than R and a fourth switching element configured, in response to a responsive to a fourth control signal, to couple the capacitor to the second through the resistor. The capacitor can be quickly charged or discharged over a period less than RC or less than 0.7 RC. The DAC may comprise a first control element configured to switch on the second switching element before switching on the first switching element and a second control element configured to switch on the fourth switching element before switching on the third switching element.
摘要翻译：描述了数模转换器（DAC）。 DAC包括具有电阻R的电阻器和具有电容C的电容器。DAC包括第一开关元件，该第一开关元件响应于第一控制信号，经由电阻小于 R和第二开关元件，其被配置为响应于第二控制信号，通过电阻器将电容器耦合到第一导轨。 DAC还包括第三开关元件，其被配置为响应于第三控制信号，经由具有小于R的电阻的路径和第四开关元件将电容器耦合到第二导轨（8），响应于响应到第四控制信号，以通过电阻将电容器耦合到第二控制信号。电容器可以在小于RC或小于0.7 RC的时间内快速充电或放电。 DAC可以包括第一控制元件，其被配置为在接通第一开关元件之前接通第二开关元件，以及第二控制元件，其被配置为在接通第三开关元件之前接通第四开关元件。

10. 发明申请

US20150263758A1 HIGH PERFORMANCE DIGITAL TO ANALOG CONVERTER 有权
标题翻译：高性能数字到模拟转换器
公开(公告)号：US20150263758A1
公开(公告)日：2015-09-17
申请号：US14638246
申请日：2015-03-04
申请人： STMICROELECTRONICS S.r.l.
发明人： Antonino Conte , Maria Giaquinta
IPC分类号： H03M1/66 , G11C16/06
CPC分类号： G11C16/06 , H03F1/34 , H03F3/347 , H03F3/45 , H03F3/45475 , H03F3/45977 , H03F2200/156 , H03F2200/375 , H03F2200/453 , H03F2203/45101 , H03F2203/45332 , H03F2203/45514 , H03F2203/45546 , H03F2203/45632 , H03M1/661
摘要： A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.
摘要翻译：数模转换器（DAC）可以包括提供第一模拟值的转换块。 DAC还可以包括用于接收第一模拟值并提供由放大因子放大的第二模拟值的放大块。放大块可以包括用于接收第一模拟值的第一输入端，第二输入端和用于提供第二模拟值的输出端。放大块还可以包括第一电容元件和第二电容元件。第一和第二电容元件可以确定放大系数。放大块还可以包括用于在第二电容元件的第一端子处恢复电荷的控制单元，并且基于该第二模拟值。

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