专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09921992B2 Asynchronous data link 有权
公开(公告)号：US09921992B2
公开(公告)日：2018-03-20
申请号：US14981478
申请日：2015-12-28
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： Julian Hilgemberg Pontes , Pascal Vivet
IPC分类号： G06F13/42 , G06F15/78 , H03K19/096
CPC分类号： G06F13/4226 , G06F13/4252 , G06F15/7825 , H03K19/0966 , Y02D10/14 , Y02D10/151
摘要： A two-phase asynchronous transmission circuit for transmitting data over a wired interface according to a two-phase asynchronous protocol, the transmission circuit including: N data output lines, where N is an integer equal to 3 or more, wherein the transmission circuit is capable of transmitting N unique data symbols, each of the output lines being associated with a corresponding one of the N data symbols, and the transmission circuit is adapted to transmit each data symbol by applying a voltage transition to the corresponding output line independently of the voltage state of the other output lines.

2. 发明授权

US09762239B2 Logic circuit, semiconductor device, electronic component, and electronic device 有权
公开(公告)号：US09762239B2
公开(公告)日：2017-09-12
申请号：US15262186
申请日：2016-09-12
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Hikaru Tamura
IPC分类号： H03K19/20 , H03K19/00
CPC分类号： H03K19/0013 , G09G3/20 , G11C7/1006 , G11C7/12 , G11C11/00 , G11C11/401 , G11C11/4094 , H01L27/10814 , H03K19/0966
摘要： A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor. The dynamic logic circuit includes a second output node. The first transistor and transistors in the dynamic logic circuit have an n-type conductivity or a p-type conductivity. The first output node is electrically connected to a first terminal of the capacitor, and the second output node is electrically connected to a second terminal of the capacitor. A first terminal of the first transistor is electrically connected to the first output node, and a first voltage is input to a second terminal of the first transistor.

3. 发明授权

US09558309B2 Timing violation resilient asynchronous template 有权
标题翻译：定时违规弹性异步模板
公开(公告)号：US09558309B2
公开(公告)日：2017-01-31
申请号：US14702426
申请日：2015-05-01
申请人： Peter A. Beerel , Melvin Breuer , Benmao Cheng , Dylan Hand
发明人： Peter A. Beerel , Melvin Breuer , Benmao Cheng , Dylan Hand
IPC分类号： H03K19/00 , G06F17/50 , H03K3/037 , H03K19/003 , H03K19/096
CPC分类号： G06F17/505 , G06F17/5031 , G06F17/5059 , G06F2217/62 , G06F2217/84 , H03K3/037 , H03K3/0375 , H03K19/003 , H03K19/00323 , H03K19/0966
摘要： An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.
摘要翻译：异步电路可以包括单轨逻辑数据通路; 一个或多个错误检测锁存器; 控制器，用于控制错误检测锁存器; 和延迟线。在错误检测锁存器指示是否发生错误之前，控制器和延迟线可以协作以与一个或多个其他控制器进行通信，即受控错误检测锁存器的输出可能是有效的。

4. 发明申请

US20160049930A1 INTEGRATED CLOCK GATER (ICG) USING CLOCK CASCODE COMPLIMENTARY SWITCH LOGIC 有权
公开(公告)号：US20160049930A1
公开(公告)日：2016-02-18
申请号：US14925949
申请日：2015-10-28
申请人： Matthew S. BERZINS , Prashant U. KENKARE
发明人： Matthew S. BERZINS , Prashant U. KENKARE
IPC分类号： H03K17/284 , H03K19/096 , H03K3/356
CPC分类号： H03K17/284 , H03K3/356 , H03K3/356104 , H03K19/00 , H03K19/0016 , H03K19/0963 , H03K19/0966
摘要： Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.

5. 发明授权

US08593176B2 One phase logic 有权
标题翻译：一相逻辑
公开(公告)号：US08593176B2
公开(公告)日：2013-11-26
申请号：US13350342
申请日：2012-01-13
申请人： Raymond Nijssen , Kamal Chaudhary , Rajit Manohar , Christopher LaFrieda , Clinton W. Kelly , Virantha Ekanayake
发明人： Raymond Nijssen , Kamal Chaudhary , Rajit Manohar , Christopher LaFrieda , Clinton W. Kelly , Virantha Ekanayake
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/0966
摘要： Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.
摘要翻译：提供了包括异步线性管线和单相管线的电路，以及形成异步线性管线电路并将其转换为单相管线电路的方法。公开了附加电路，系统和方法。

6. 发明申请

US20130249596A1 INACTIVITY TRIGGERED SELF CLOCKING LOGIC FAMILY 有权
标题翻译：不活动触发自锁定逻辑系列
公开(公告)号：US20130249596A1
公开(公告)日：2013-09-26
申请号：US13426776
申请日：2012-03-22
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, JR. , Sebastian T. Ventrone , Charles S. Woodruff
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, JR. , Sebastian T. Ventrone , Charles S. Woodruff
IPC分类号： H03K19/00
CPC分类号： H03K19/0966 , H03K19/0013
摘要： Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.
摘要翻译：电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中只有在本地逻辑设备中已经满足设置时间之后）。这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

7. 发明授权

US08335291B2 Semiconductor device, a parallel interface system and methods thereof 有权
标题翻译：半导体器件，并行接口系统及其方法
公开(公告)号：US08335291B2
公开(公告)日：2012-12-18
申请号：US12929627
申请日：2011-02-04
申请人： Seung-Jun Bae , Seong-Jin Jang , Beom-Sig Cho
发明人： Seung-Jun Bae , Seong-Jin Jang , Beom-Sig Cho
IPC分类号： H04L7/00
CPC分类号： G11C7/22 , H03K19/0966 , H04L7/0008 , H04L7/033 , H04L7/10
摘要： A semiconductor device, a parallel interface system and methods thereof are provided. The example semiconductor device may include a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode. An example method may include reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.
摘要翻译：提供半导体器件，并行接口系统及其方法。示例性半导体器件可以包括产生参考时钟信号的参考时钟发送块，多个第一收发器块，多个第一收发器块中的每一个基于多个相位控制的多个第一收发器块中的一个发送至少一个并行数据位信号传输采样时钟信号和控制发射采样时钟信号的相位的每引脚偏移校正块，以产生相应的多个收发器模块的相位控制的采样时钟信号，每个引脚的去偏移块控制每个相位 - 基于相对于给定的第一收发器块的多个训练数据位信号中的给定训练数据位信号与第一操作模式中的参考时钟信号之间的相位偏移以及基于相位偏移的受控发送采样时钟信号与至少一个并行数据的给定并行数据位信号之间的相位偏移有关的信息在第二操作模式中的位信号和参考时钟信号。示例性方法可以包括基于在第一操作模式中的多个发送的训练数据比特信号与对应的多个接收的训练数据比特信号之间的比较来减少偏斜，并且基于接收到的相位偏移相关的相位偏移信息减少偏斜在第二操作模式中参考信号和并行数据位信号之间的差异。

8. 发明授权

US08324938B2 Self-timed trigger circuit with single-rail data input 有权
标题翻译：具有单轨数据输入的自定时触发电路
公开(公告)号：US08324938B2
公开(公告)日：2012-12-04
申请号：US12937909
申请日：2009-04-13
申请人： Igor Anatolievich Sokolov , Yury Afanasievich Stepchenkov , Yury Georgievich Dyachenko
发明人： Igor Anatolievich Sokolov , Yury Afanasievich Stepchenkov , Yury Georgievich Dyachenko
IPC分类号： H03K19/20 , H03K19/173
CPC分类号： H03K3/027 , H03K19/0966
摘要： A self-timed implementation of single-stage and two-stage self-timed trigger circuits with single-rail data input is provided. This is achieved by a circuit containing storage unit with element indicating transition termination, single-rail data input, control input, data output, and indication output, into which a conversion unit is added which converts single-rail data input and control input signals and has data input, control input, data output and control output. An additional feedback output allows for speeding-up transition of device, which is a source of the single-rail data input of the trigger.
摘要翻译：提供了具有单轨数据输入的单级和两级自定时触发电路的自定时实现。这是通过包含存储单元的电路来实现的，该存储单元具有指示转移终止，单轨数据输入，控制输入，数据输出和指示输出的元件，其中添加有转换单轨数据输入和控制输入信号的转换单元，具有数据输入，控制输入，数据输出和控制输出。额外的反馈输出允许加速设备的转换，这是触发器的单轨数据输入的源。

9. 发明申请

US20110121877A1 SELF-TIMED RS-TRIGGER WITH THE ENHANCED NOISE IMMUNITY 有权
标题翻译：自锁RS-TRIGGER与增强的噪声免疫
公开(公告)号：US20110121877A1
公开(公告)日：2011-05-26
申请号：US13055170
申请日：2010-05-28
申请人： Igor Anatolievich Sokolov , Yury Afanasievich Stephchenkov , Yury Georgievich Dyachenko
发明人： Igor Anatolievich Sokolov , Yury Afanasievich Stephchenkov , Yury Georgievich Dyachenko
IPC分类号： H03K3/037
CPC分类号： H03K19/0966
摘要： The invention describes self-timed RS-trigger with the enhanced noise immunity. Declared effect is achieved due to that circuit containing storage unit (1), indication unit (2), paraphase data input (3, 4), paraphase data output (5, 6), and indication output (7), is modified by adding two inverters (8, 9) and preindication unit (10). Inverters increase output capability of the trigger's paraphase data output and provide an electric isolation of the outputs of the storage unit from an external environment that leads to increasing immunity of the data stored in the trigger to influence of noises at signal wires. The preindication unit provides the trigger's indicatability.
摘要翻译：本发明描述了具有增强的抗噪声能力的自定时RS触发器。由于包含存储单元（1），指示单元（2），后期数据输入（3,4），后期数据输出（5,6）和指示输出（7）的电路通过添加来修改声明效果两个逆变器（8,9）和预处理单元（10）。逆变器增加触发器的后期数据输出的输出能力，并且提供存储单元的输出与外部环境的电隔离，这导致存储在触发器中的数据的增强的抗扰性对信号线上的噪声的影响。预警单元提供触发器的可指示性。

10. 发明申请

US20110043252A1 SELF-TIMED TRIGGER WITH SINGLE-RAIL DATA INPUT 有权
标题翻译：具有单轨数据输入的自定位触发器
公开(公告)号：US20110043252A1
公开(公告)日：2011-02-24
申请号：US12937909
申请日：2009-04-13
申请人： Igor Anatolievich sokolov , Yury Afanasievich Stepchenkov , Yury Georgievich Dyachenko
发明人： Igor Anatolievich sokolov , Yury Afanasievich Stepchenkov , Yury Georgievich Dyachenko
IPC分类号： H03K19/20 , H03K3/00
CPC分类号： H03K3/027 , H03K19/0966
摘要： A self-timed implementation of single-stage and two-stage self-timed triggers with single-rail data input is provided. This is achieved by a circuit containing storage unit with element indicating transition termination, single-rail data input, control input, data output, and indication output, into which a conversion unit is added which converts single-rail data input and control input signals and has data input, control input, data output and control output. An additional feedback output allows for speeding-up transition of device, which is a source of the single-rail data input of the trigger.
摘要翻译：提供了具有单轨数据输入的单阶段和两阶段自定时触发器的自定时实现。这是通过包含存储单元的电路来实现的，该存储单元具有指示转移终止，单轨数据输入，控制输入，数据输出和指示输出的元件，其中添加有转换单轨数据输入和控制输入信号的转换单元，具有数据输入，控制输入，数据输出和控制输出。额外的反馈输出允许加速设备的转换，这是触发器的单轨数据输入的源。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式