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1. 发明授权

US08098086B2 Integrated circuit and programmable delay 有权
标题翻译：集成电路和可编程延时
公开(公告)号：US08098086B2
公开(公告)日：2012-01-17
申请号：US12939468
申请日：2010-11-04
申请人： Kazimierz Szczypinski
发明人： Kazimierz Szczypinski
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , G11C7/22 , G11C7/222 , H03K5/133 , H03K2005/00104 , H03K2005/00123 , H03K2005/00241
摘要： Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element.
摘要翻译：集成电路和可编程延时。一个实施例提供了包括具有多个单个延迟单元的可编程延迟元件的集成电路。延迟单元包括第一输入和第二输入以及第一输出。延迟单元被布置成形成链，使得先前延迟单元的第一输出耦合到连续延迟单元的第二输入。任何延迟单元的第一输入被配置为接收待延迟的输入信号。多个延迟单元中的延迟单元被配置为构成包括布置在起始点下游的任何延迟单元的信号路径的起始点。链中最后一个延迟单元的第一个输出形成可编程延迟元件的输出。

2. 发明授权

US08044696B2 Delay circuit having long delay time and semiconductor device comprising the same 有权
标题翻译：具有长延迟时间的延迟电路和包括该延迟电路的半导体器件
公开(公告)号：US08044696B2
公开(公告)日：2011-10-25
申请号：US12391959
申请日：2009-02-24
申请人： Tae-Hyung Kim , Min-Su Kim
发明人： Tae-Hyung Kim , Min-Su Kim
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00123 , H03K2217/0018
摘要： A delay circuit has a long delay time and a semiconductor device includes the delay circuit. The delay circuit includes an inverter circuit unit having at least one inverter. Each of the inverters includes a first transistor connected to a supply voltage and a second transistor connected to a ground voltage. The inverter circuit unit receives a first signal and outputs a second signal by delaying the first signal. At least one capacitor unit is connected to an input terminal of the inverter such that a loading capacitance of the inverter circuit unit is increased.
摘要翻译：延迟电路具有较长的延迟时间，半导体器件包括延迟电路。延迟电路包括具有至少一个逆变器的逆变器电路单元。每个反相器包括连接到电源电压的第一晶体管和连接到接地电压的第二晶体管。逆变器电路单元接收第一信号并通过延迟第一信号输出第二信号。至少一个电容器单元连接到逆变器的输入端子，使得逆变器电路单元的负载电容增加。

3. 发明申请

US20110057699A1 INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY 有权
标题翻译：集成电路和可编程延迟
公开(公告)号：US20110057699A1
公开(公告)日：2011-03-10
申请号：US12939468
申请日：2010-11-04
申请人： Kazimierz Szczypinski
发明人： Kazimierz Szczypinski
IPC分类号： H03L7/00 , H03H11/26
CPC分类号： H03K5/135 , G11C7/22 , G11C7/222 , H03K5/133 , H03K2005/00104 , H03K2005/00123 , H03K2005/00241
摘要： Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element.
摘要翻译：集成电路和可编程延迟。一个实施例提供了包括具有多个单个延迟单元的可编程延迟元件的集成电路。延迟单元包括第一输入和第二输入以及第一输出。延迟单元被布置成形成链，使得先前延迟单元的第一输出耦合到连续延迟单元的第二输入。任何延迟单元的第一输入被配置为接收待延迟的输入信号。多个延迟单元中的延迟单元被配置为构成包括布置在起始点下游的任何延迟单元的信号路径的起始点。链中最后一个延迟单元的第一个输出形成可编程延迟元件的输出。

4. 发明申请

US20100231258A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20100231258A1
公开(公告)日：2010-09-16
申请号：US12563389
申请日：2009-09-21
申请人： Hitoshi Iwai
发明人： Hitoshi Iwai
IPC分类号： H03K19/0175 , G11C19/00 , H03K19/20
CPC分类号： G11C19/285 , H03K5/133 , H03K5/15026 , H03K2005/00123 , H03K2005/00143
摘要： A semiconductor integrated circuit includes logic circuits connected in a plurality of stages, a voltage-level inverting unit that is inserted in a signal transmission path of the logic circuits and inverts a voltage level input to the logic circuits, and an inversion-timing control unit that controls inversion timing for the voltage level inverted by the voltage-level inverting unit.
摘要翻译：半导体集成电路包括以多级连接的逻辑电路，电压电平反转单元，其插入在逻辑电路的信号传输路径中并使输入到逻辑电路的电压电平反相;以及反相定时控制单元其控制由电压电平反转单元反相的电压电平的反相定时。

5. 发明授权

US07692459B2 High resolution delay adjustor 有权
标题翻译：高分辨率延时调节器
公开(公告)号：US07692459B2
公开(公告)日：2010-04-06
申请号：US11878411
申请日：2007-07-24
申请人： Chao-Cheng Lee
发明人： Chao-Cheng Lee
IPC分类号： H03H9/38 , H03M1/12
CPC分类号： H03K5/131 , H03K2005/00117 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A delay adjustor for adjusting the delay time of a signal, the adjustor comprising: a first capacitance unit and a variable capacitance unit serially coupled to the first capacitor wherein the capacitance of the variable capacitance unit is adjusted according to a first control signal and the variable capacitance unit comprises a plurality of second capacitors and at least a first switch coupled to the at least one capacitor of the second capacitors.
摘要翻译：一种用于调整信号的延迟时间的延迟调整器，所述调整器包括：第一电容单元和串联耦合到所述第一电容器的可变电容单元，其中根据第一控制信号调整所述可变电容单元的电容，电容单元包括多个第二电容器和耦合到第二电容器的至少一个电容器的至少第一开关。

6. 发明申请

US20100045351A1 INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY 有权
标题翻译：集成电路和可编程延迟
公开(公告)号：US20100045351A1
公开(公告)日：2010-02-25
申请号：US12195120
申请日：2008-08-20
申请人： Kazimierz Szczypinski
发明人： Kazimierz Szczypinski
IPC分类号： H03L7/00 , H03H11/26 , H03K3/00
CPC分类号： H03K5/135 , G11C7/22 , G11C7/222 , H03K5/133 , H03K2005/00104 , H03K2005/00123 , H03K2005/00241
摘要： Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element.
摘要翻译：集成电路和可编程延时。一个实施例提供了包括具有多个单个延迟单元的可编程延迟元件的集成电路。延迟单元包括第一输入和第二输入以及第一输出。延迟单元被布置成形成链，使得先前延迟单元的第一输出耦合到连续延迟单元的第二输入。任何延迟单元的第一输入被配置为接收待延迟的输入信号。多个延迟单元中的延迟单元被配置为构成包括布置在起始点下游的任何延迟单元的信号路径的起始点。链中最后一个延迟单元的第一个输出形成可编程延迟元件的输出。

7. 发明申请

US20090212838A1 Delay Circuit Having Long Delay Time and Semiconductor Device Comprising the Same 有权
标题翻译：具有长延迟时间的延迟电路和包括其的半导体器件
公开(公告)号：US20090212838A1
公开(公告)日：2009-08-27
申请号：US12391959
申请日：2009-02-24
申请人： Tae-Hyung Kim , Min-Su Kim
发明人： Tae-Hyung Kim , Min-Su Kim
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00123 , H03K2217/0018
摘要： A delay circuit has a long delay time and a semiconductor device includes the delay circuit. The delay circuit includes an inverter circuit unit having at least one inverter. Each of the inverters includes a first transistor connected to a supply voltage and a second transistor connected to a ground voltage. The inverter circuit unit receives a first signal and outputs a second signal by delaying the first signal. At least one capacitor unit is connected to an input terminal of the inverter such that a loading capacitance of the inverter circuit unit is increased.
摘要翻译：延迟电路具有较长的延迟时间，半导体器件包括延迟电路。延迟电路包括具有至少一个逆变器的逆变器电路单元。每个反相器包括连接到电源电压的第一晶体管和连接到接地电压的第二晶体管。逆变器电路单元接收第一信号并通过延迟第一信号输出第二信号。至少一个电容器单元连接到逆变器的输入端子，使得逆变器电路单元的负载电容增加。

8. 发明申请

US20090160562A1 OSCILLATING DEVICE 审中-公开
标题翻译：振荡装置
公开(公告)号：US20090160562A1
公开(公告)日：2009-06-25
申请号：US12193042
申请日：2008-08-17
申请人： Hsien-Sheng Huang
发明人： Hsien-Sheng Huang
IPC分类号： H03L1/00 , H03B5/12 , H03K3/03
CPC分类号： H03K3/0315 , H03K3/011 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143 , H03K2005/00202 , H03L1/00
摘要： The present invention provides an oscillating device. The oscillating device includes: a voltage regulating module, a current generating module, and an oscillating module. The voltage regulating module is utilized for generating a control voltage at an output terminal, and the voltage regulating module includes: a first operational amplifier, a first switch element, and a first voltage dividing circuit. The oscillating module includes: a plurality of switch modules connected in series, a current mirror module, and a plurality of capacitor modules. In the oscillating device of the present invention, a frequency of an oscillating signal outputted by the oscillating module will not be affected by voltage offset of an operating voltage, environment temperature variations, or semiconductor process variations.
摘要翻译：本发明提供一种摆动装置。振荡装置包括：电压调节模块，电流产生模块和振荡模块。电压调节模块用于在输出端产生控制电压，电压调节模块包括：第一运算放大器，第一开关元件和第一分压电路。振荡模块包括：串联连接的多个开关模块，电流镜模块和多个电容器模块。在本发明的振荡装置中，由振荡模块输出的振荡信号的频率不受工作电压，环境温度变化或半导体工艺变化的电压偏移的影响。

9. 发明授权

US07236034B2 Self correcting scheme to match pull up and pull down devices 有权
标题翻译：自校正方案，以配合拉拔设备
公开(公告)号：US07236034B2
公开(公告)日：2007-06-26
申请号：US10901833
申请日：2004-07-27
申请人： Wayne T. Chen , Narasimhan R. Trichy
发明人： Wayne T. Chen , Narasimhan R. Trichy
IPC分类号： H03H11/06
CPC分类号： H03K19/00323 , H03K2005/00097 , H03K2005/00123 , H04L25/0272
摘要： The self correcting scheme to match pull up and pull down devices includes: a first comparator for comparing a common mode signal to a high reference limit; a second comparator for comparing the common mode signal to a low reference limit; a first flip flop having an input coupled to an output of the first comparator; a second flip flop having an input coupled to an output of the second comparator; a counter having inputs coupled to the first and second flip flops; and a delay device controlled by an output of the counter, wherein the delay device provides a pull down control signal that is delayed relative to a pull up control signal.
摘要翻译：匹配上拉和下拉器件的自校正方案包括：用于将共模信号与高参考极限进行比较的第一比较器; 第二比较器，用于将共模信号与低参考极限进行比较; 第一触发器，其具有耦合到所述第一比较器的输出的输入; 第二触发器，具有耦合到第二比较器的输出的输入; 具有耦合到第一和第二触发器的输入的计数器; 以及由计数器的输出控制的延迟装置，其中延迟装置提供相对于上拉控制信号延迟的下拉控制信号。

10. 发明申请

US20060022735A1 Self correcting scheme to match pull up and pull down devices 有权
标题翻译：自校正方案，以配合拉拔设备
公开(公告)号：US20060022735A1
公开(公告)日：2006-02-02
申请号：US10901833
申请日：2004-07-27
申请人： Wayne Chen , Narasimhan Trichy
发明人： Wayne Chen , Narasimhan Trichy
IPC分类号： H03H11/26
CPC分类号： H03K19/00323 , H03K2005/00097 , H03K2005/00123 , H04L25/0272
摘要： The self correcting scheme to match pull up and pull down devices includes: a first comparator for comparing a common mode signal to a high reference limit; a second comparator for comparing the common mode signal to a low reference limit; a first flip flop having an input coupled to an output of the first comparator; a second flip flop having an input coupled to an output of the second comparator; a counter having inputs coupled to the first and second flip flops; and a delay device controlled by an output of the counter, wherein the delay device provides a pull down control signal that is delayed relative to a pull up control signal.
摘要翻译：匹配上拉和下拉器件的自校正方案包括：用于将共模信号与高参考极限进行比较的第一比较器; 第二比较器，用于将共模信号与低参考极限进行比较; 第一触发器，其具有耦合到所述第一比较器的输出的输入; 第二触发器，具有耦合到第二比较器的输出的输入; 具有耦合到第一和第二触发器的输入的计数器; 以及由计数器的输出控制的延迟装置，其中延迟装置提供相对于上拉控制信号延迟的下拉控制信号。

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