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1. 发明授权

US09837992B2 Semiconductor device 有权
公开(公告)号：US09837992B2
公开(公告)日：2017-12-05
申请号：US15077438
申请日：2016-03-22
申请人： Hyun-Chul Hwang , Min-Su Kim
发明人： Hyun-Chul Hwang , Min-Su Kim
IPC分类号： H03K3/289 , H03K3/012 , H03K3/356
CPC分类号： H03K3/012 , H03K3/356191
摘要： A semiconductor circuit includes a first circuit determining a voltage of a first node in response to the clock signal and the input data signal, a first latch determining a voltage of a second node in response to the clock signal and the voltage of the first node, and a second circuit determining a voltage of a third node in response to the clock signal and the voltage of the second node. The output data signal is provided in response to the voltage of the third node, the clock signal controls a flip-flop operation with respect to the input data signal and the output data signal, and respective voltages are maintained constant at the first node, second node and third node regardless of level transitions in the clock signal so long as a level of the input data signal is maintained constant.

2. 发明申请

US20160285435A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160285435A1
公开(公告)日：2016-09-29
申请号：US15077438
申请日：2016-03-22
申请人： HYUN-CHUL HWANG , MIN-SU KIM
发明人： HYUN-CHUL HWANG , MIN-SU KIM
IPC分类号： H03K3/012 , H03K3/356
CPC分类号： H03K3/012 , H03K3/356191
摘要： A semiconductor circuit includes a first circuit determining a voltage of a first node in response to the clock signal and the input data signal, a first latch determining a voltage of a second node in response to the clock signal and the voltage of the first node, and a second circuit determining a voltage of a third node in response to the clock signal and the voltage of the second node. The output data signal is provided in response to the voltage of the third node, the clock signal controls a flip-flop operation with respect to the input data signal and the output data signal, and respective voltages are maintained constant at the first node, second node and third node regardless of level transitions in the clock signal so long as a level of the input data signal is maintained constant.
摘要翻译：半导体电路包括响应于时钟信号和输入数据信号确定第一节点的电压的第一电路，响应于时钟信号和第一节点的电压确定第二节点的电压的第一锁存器，以及响应于所述时钟信号和所述第二节点的电压确定第三节点的电压的第二电路。输出数据信号响应于第三节点的电压被提供，时钟信号控制相对于输入数据信号和输出数据信号的触发器操作，并且各个电压在第一节点保持恒定，第二节点和第三节点，而不管时钟信号中的电平转换如何，只要输入数据信号的电平保持恒定即可。

3. 发明授权

US09450584B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09450584B2
公开(公告)日：2016-09-20
申请号：US14870351
申请日：2015-09-30
申请人： Min-Su Kim
发明人： Min-Su Kim
IPC分类号： H03K19/0175 , H03K19/0185 , H03K19/20 , H03K3/356
CPC分类号： H03K19/018507 , H03K3/012 , H03K3/356 , H03K3/356173 , H03K19/0016 , H03K19/20
摘要： A semiconductor device includes a first circuit applying an enable signal having a first logic level and a clock signal having the first logic level, supplying a first voltage to a first node and converting a voltage level of the first node into a second logic level different from the first logic level, and a second circuit applying an enable signal having the second logic level and a clock signal having the first logic level, supplying a second voltage to a second node different from the first node and converting a voltage level of the second node into the second logic level. The second circuit includes an operation circuit performing a NAND operation on the logic level of the enable signal and the voltage level of the second node, and a switch turned on in response to an output of the operation circuit and supplying the second voltage to the second node.
摘要翻译：半导体器件包括施加具有第一逻辑电平的使能信号和具有第一逻辑电平的时钟信号的第一电路，向第一节点提供第一电压并将第一节点的电压电平转换成不同于第一逻辑电平的第二逻辑电平第一逻辑电平，以及施加具有第二逻辑电平的使能信号和具有第一逻辑电平的时钟信号的第二电路，向不同于第一节点的第二节点提供第二电压，并且转换第二节点的电压电平进入第二个逻辑水平。第二电路包括对使能信号的逻辑电平和第二节点的电压电平执行NAND运算的运算电路，以及响应于运算电路的输出而导通的开关，并将第二电压提供给第二电路节点。

4. 发明授权

US09209491B2 Stack/folding-typed electrode assembly and method for preparation of the same 有权
标题翻译：堆叠/折叠型电极组件及其制备方法
公开(公告)号：US09209491B2
公开(公告)日：2015-12-08
申请号：US12747671
申请日：2008-12-12
申请人： KiJae Kim , Min Su Kim
发明人： KiJae Kim , Min Su Kim
IPC分类号： H01M2/20 , H01M10/0583 , H01M2/16 , H01M2/18 , H01M10/04 , H01M10/0525
CPC分类号： H01M10/0583 , H01M2/1653 , H01M2/1673 , H01M2/18 , H01M10/0459 , H01M10/0525 , Y02E60/122 , Y02T10/7011 , Y10T29/49108
摘要： Disclosed herein is an electrode assembly constructed in a structure in which a plurality of electrochemical cells, formed of full cells having a cathode/separator/anode structure, as basic units, are overlapped, and a continuous separator sheet is disposed between the overlapped electrochemical cells, wherein a unit electrode surrounded by the separator sheet is located at a middle of the overlapped electrochemical cells, which is a winding start point, and the full cells disposed above and below the unit electrode are symmetrical to each other about the unit electrode in the direction of electrodes of the full cells. The electrode assembly is manufactured with high productivity while the electrode assembly exhibits performance and safety equal to those of a conventional stack/folding type electrode assembly.
摘要翻译：本文公开了一种电极组件，其结构是将由具有阴极/隔板/阳极结构的全电池形成的多个电化学电池作为基本单元重叠的结构，并且在重叠的电化学电池之间设置连续的隔离片其特征在于，由所述隔离片包围的单位电极位于所述重叠的电化学电池的中间，所述重叠的电化学电池为绕线起点，并且设置在所述单位电极的上下的全电池在所述单电极的所述单电极中彼此对称全细胞电极方向。电极组件以高生产率制造，而电极组件的性能和安全性与传统的堆叠/折叠型电极组件的性能和安全性相当。

5. 发明申请

US20150207494A1 SEMICONDUCTOR CIRCUIT AND METHOD OF OPERATING THE CIRCUIT 有权
标题翻译：半导体电路和操作电路的方法
公开(公告)号：US20150207494A1
公开(公告)日：2015-07-23
申请号：US14645818
申请日：2015-03-12
申请人： Min-Su KIM
发明人： Min-Su KIM
IPC分类号： H03K3/012 , H03K3/356
CPC分类号： H03K3/012 , G01R31/318541 , H03K3/356104 , H03K3/356139
摘要： Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal, a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal, a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal, a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node, and a control circuit included in at least one of the first to third circuits and the latch and configured to receive the control signal.
摘要翻译：提供一种半导体电路，其包括：第一电路，被配置为基于输入数据的电压电平，锁存输入节点的电压电平和时钟信号的电压电平来确定反馈节点的电压电平;第二电路配置为基于所述时钟信号的电压电平对所述锁存器输入节点进行预充电，第三电路被配置为基于所述反馈节点的电压电平和所述时钟信号的电压电平来下拉所述锁存器输入节点;锁存器被配置为基于所述时钟信号的电压电平和所述锁存输入节点的电压电平输出输出数据，以及包括在所述第一至第三电路和所述锁存器中的至少一个中的控制电路，并且被配置为接收所述控制信号。

6. 发明申请

US20150036447A1 FLIP-FLOP WITH ZERO-DELAY BYPASS MUX 有权
标题翻译：带有零延迟旁路多路复用器的FLIP-FLOP
公开(公告)号：US20150036447A1
公开(公告)日：2015-02-05
申请号：US14202821
申请日：2014-03-10
申请人： Christina WELLS , Matt BERZINS , Min Su KIM
发明人： Christina WELLS , Matt BERZINS , Min Su KIM
IPC分类号： H03K5/04 , G11C29/02 , G11C5/14
CPC分类号： H03K5/04 , G11C29/12015
摘要： Exemplary embodiments may disclose a flip-flop circuit for inserting a zero-delay bypass mux including a master circuit which is configured to receive a data input, an input clock signal, and a bypass signal, and output an intermediate signal to a first node; and a slave circuit which is configured to receive the intermediate signal at the first node, the input clock signal, and the bypass signal, and output an output clock signal. The bypass signal controls the slave circuit to output one of a buffered input clock signal and a stretched clock signal as the output clock signal based on a logic level of the bypass signal.
摘要翻译：示例性实施例可以公开一种用于插入包括被配置为接收数据输入的主电路的零延迟旁路复用器的触发器电路，输入时钟信号和旁路信号，并将中间信号输出到第一节点; 以及被配置为在第一节点处接收中间信号的从属电路，输入时钟信号和旁路信号，并输出输出时钟信号。旁路信号控制从电路根据旁路信号的逻辑电平输出缓冲输入时钟信号和延时时钟信号之一作为输出时钟信号。

7. 发明授权

US08936873B2 Cathode active material and lithium secondary battery containing them 有权
标题翻译：阴极活性物质和锂二次电池
公开(公告)号：US08936873B2
公开(公告)日：2015-01-20
申请号：US12728874
申请日：2010-03-22
申请人： Ji Heon Ryu , Min Su Kim , Jung Eun Hyun , Jaepil Lee , Eun Ju Lee , Youngjoon Shin
发明人： Ji Heon Ryu , Min Su Kim , Jung Eun Hyun , Jaepil Lee , Eun Ju Lee , Youngjoon Shin
IPC分类号： H01M4/13 , H01M4/50 , H01M4/58 , H01M4/525 , H01M4/36 , H01M4/505 , H01M10/0525
CPC分类号： H01M4/364 , H01M4/505 , H01M4/525 , H01M10/052 , H01M10/0525 , H01M2004/028 , Y02E60/122 , Y02T10/7011
摘要： Provided is a non-aqueous electrolyte-based, high-power lithium secondary battery having a long service life and superior safety at both room temperature and high temperature, even after repeated high-current charging and discharging. The battery comprises a mixture of a lithium/manganese spinel oxide having a substitution of a manganese (Mn) site with a certain metal ion and a lithium/nickel/cobalt/manganese composite oxide, as a cathode active material.
摘要翻译：本发明提供一种即使在反复进行大电流充放电之后，在室温和高温下也具有使用寿命长，安全性高的非水电解质型大功率锂二次电池。该电池包括用锰（Mn）位置取代某种金属离子的锂/锰尖晶石氧化物和锂/镍/钴/锰复合氧化物的混合物作为阴极活性材料。

8. 发明申请

US20140266364A1 SEMICONDUCTOR CIRCUIT AND METHOD OF OPERATING THE SAME 有权
标题翻译：半导体电路及其操作方法
公开(公告)号：US20140266364A1
公开(公告)日：2014-09-18
申请号：US13844242
申请日：2013-03-15
申请人： Rahul SINGH , Min-Su KIM
发明人： Rahul SINGH , Min-Su KIM
IPC分类号： H03K3/3562
CPC分类号： H03K3/356121
摘要： Provided are a semiconductor circuit and a method of operating the same. The semiconductor circuit includes a first pulse generating circuit enabled to a rising edge of a clock signal and configured to generate a first read pulse, a second pulse generating circuit enabled to a rising edge of the clock signal and configured to generate a second read pulse independent of the first read pulse, a dynamic pull-down stage configured to develop a voltage level of a first dynamic node based at least on data values of an input signal and the first and second read pulses, and a dynamic pull-up stage configured to develop a voltage level of a second dynamic node based at least on data values of the input signal and the first and second read pulses.
摘要翻译：提供半导体电路及其操作方法。该半导体电路包括：第一脉冲发生电路，其能够进入时钟信号的上升沿，并被配置为产生第一读取脉冲，第二脉冲发生电路使能到时钟信号的上升沿并被配置为产生独立的第二读取脉冲所述动态下拉阶段被配置为至少基于输入信号和所述第一和第二读取脉冲的数据值来开发第一动态节点的电压电平;以及动态上拉阶段，被配置为至少基于输入信号和第一和第二读取脉冲的数据值来开发第二动态节点的电压电平。

9. 发明授权

US08795883B2 Secondary battery with advanced safety 有权
标题翻译：二次电池安全性高
公开(公告)号：US08795883B2
公开(公告)日：2014-08-05
申请号：US11555743
申请日：2006-11-02
申请人： Youngjoon Shin , Min Su Kim , Junill Yoon , Ji Heon Ryu , Jeong Hee Choi , Seung-Jin Yang
发明人： Youngjoon Shin , Min Su Kim , Junill Yoon , Ji Heon Ryu , Jeong Hee Choi , Seung-Jin Yang
IPC分类号： H01M2/02 , H01M2/08
CPC分类号： H01M2/06 , H01M2/02 , H01M2/021 , H01M2/0275 , H01M2/0277 , H01M2/0287 , H01M2/20 , H01M2/266 , H01M2/30 , H01M10/052
摘要： Disclosed herein is a secondary battery constructed in a structure in which an electrode assembly having a cathode/separator/anode arrangement is mounted in a battery case made of a laminate sheet including a resin layer and a metal layer, electrode tabs of the electrode assembly are coupled to corresponding electrode leads, and the electrode assembly is sealed in the battery case while electrode leads are exposed to the outside of the battery case, wherein a protective film is attached to coupling regions between the electrode tabs and the electrode leads for sealing the coupling regions between the electrode tabs and the electrode leads. The secondary battery according to the present invention is constructed in a structure in which the coupling regions are sealed by the protective film, unlike a conventional secondary battery constructed in a structure in which the coupling regions between the electrode tabs and the electrode leads are exposed in the battery case. As a result, the electrode leads are protected from external impacts, such as falling of the battery. Consequently, no internal short circuit occurs, and therefore, the safety of the battery is increased.
摘要翻译：本文公开了一种二次电池，其结构是将具有阴极/隔板/阳极布置的电极组件安装在由包括树脂层和金属层的层压片制成的电池壳中，电极组件的电极片耦合到相应的电极引线，并且电极组件被密封在电池壳体中，同时电极引线暴露于电池壳体的外部，其中保护膜附接到电极接线片和电极引线之间的耦合区域，用于密封耦合电极片和电极引线之间的区域。根据本发明的二次电池被构造成其中耦合区域被保护膜密封的结构不同于传统的二次电池，其结构是将电极接头和电极引线之间的耦合区域暴露在其中电池盒。结果，电极引线被保护免受外部冲击，例如电池的掉落。因此，不会发生内部短路，因此电池的安全性增加。

10. 发明授权

US08755008B2 Polarizer and liquid crystal display using the same 有权
标题翻译：偏光镜和液晶显示器使用相同
公开(公告)号：US08755008B2
公开(公告)日：2014-06-17
申请号：US13431702
申请日：2012-03-27
申请人： Jae-Hong Park , Jong-Sung Park , Min-Su Kim , Sung-Hyun Kim
发明人： Jae-Hong Park , Jong-Sung Park , Min-Su Kim , Sung-Hyun Kim
IPC分类号： G02F1/1335
CPC分类号： G02B5/3033 , G02B1/105 , G02B1/11 , G02B1/14 , G02B1/16 , G02F1/133528 , G02F1/13452
摘要： Disclosed is a liquid crystal display and a polarizing plate used in the same. The liquid crystal display includes a liquid crystal cell and a first polarizing plate and a second polarizing plate respectively provided on each side of the liquid crystal cell. The first polarizing plate and the second polarizing plate each includes a polyvinyl alcohol polarizing film and protective films provided on both sides of the polyvinyl alcohol polarizing film, the protective films that are provided on surfaces opposite to the liquid crystal cell the first polarizing plate and the second polarizing plate each has the vapor transmissivity of 100 g/m Day or less, and the protective films that are provided on surfaces abutting the liquid crystal cell of the first polarizing plate and the second polarizing plate each has the vapor transmissivity of more than 1,500 g/m Day. When the protective films that are provided on surfaces opposite to the liquid crystal cell of the first polarizing plate and the second polarizing plate each has a UV absorption ability, the protective films that are provided on surfaces abutting the liquid crystal cell of the first polarizing plate and the second polarizing plate each has the vapor transmissivity of more than 200 g/m Day.
摘要翻译：公开了一种液晶显示器和偏光板。液晶显示器包括分别设置在液晶单元的每一侧的液晶单元和第一偏振板和第二偏振板。第一偏振板和第二偏振板各自包括聚乙烯醇偏振片和设置在聚乙烯醇偏振片两侧的保护膜，保护膜设置在与液晶单元相反的表面上，第一偏振片和第二偏光板的蒸气透过率为100g / m以下，并且设置在与第一偏振片和第二偏光板的液晶单元抵接的面上的保护膜的蒸气透过率为1500以上 g / m天。当设置在与第一偏振片和第二偏振片的液晶单元相对的表面上的保护膜各自具有UV吸收能力时，设置在与第一偏振板的液晶单元相邻的表面上的保护膜并且第二偏振板各自具有大于200g / m 2日的蒸汽透过率。

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