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1. 发明授权

US08471739B2 Digital analog converter and method for calibrating sources thereof 失效
标题翻译：数字模拟转换器及其源的校准方法
公开(公告)号：US08471739B2
公开(公告)日：2013-06-25
申请号：US13312449
申请日：2011-12-06
申请人： Jang Hong Choi , Hyun Kyu Yu
发明人： Jang Hong Choi , Hyun Kyu Yu
IPC分类号： H03M1/10
CPC分类号： H03M1/0653 , H03M1/685 , H03M1/747
摘要： Provided is a digital analog converter that output currents having different magnitudes for a digital input value according to a mapping table. The digital analog converter includes: a plurality of current sources; and a calibration unit configured to sort index values for identifying the plurality of current sources according to current magnitudes of the current sources, couple each two current sources which are symmetrical left and right about the center of the sorted index values, and map the current source pairs into a mapping table.
摘要翻译：提供了一种数字模拟转换器，其根据映射表输出对数字输入值具有不同幅度的电流。数字模拟转换器包括：多个电流源; 以及校准单元，被配置为根据当前源的当前幅度对用于识别多个电流源的索引值进行排序，将关于分选的索引值的中心的左右对称的两个电流源耦合，并且将当前源成对映射表。

2. 发明授权

US07394414B2 Error reduction in a digital-to-analog (DAC) converter 有权
标题翻译：数模转换（DAC）转换器的误差减小
公开(公告)号：US07394414B2
公开(公告)日：2008-07-01
申请号：US11587105
申请日：2005-04-11
申请人： Joseph Briaire
发明人： Joseph Briaire
IPC分类号： H03M1/10
CPC分类号： H03M1/0653 , H03M1/742
摘要： In a method to improve error reduction in a digital-to-analog converter (DAC), comprising a mapping matrix block and a plurality of selectable source units which supply signals that in combination provide for analog output signals, mapping input signals, obtained from digital input signals to be converted into the analog output signals, are supplied to the mapping matrix block. In the mapping matrix block mapping output signals are generated in response to said mapping input signals and to mapping control signals derived from errors occurring in the plurality of selectable source units. At least one of the mapping input signals is applied for the substantially simultaneous generation of the mapping output signals for a number of source units.
摘要翻译：在一种用于改善数模转换器（DAC）中的误差减小的方法中，包括映射矩阵块和多个可选择的源单元，其提供组合提供模拟输出信号的信号，映射从数字要转换为模拟输出信号的输入信号，被提供给映射矩阵块。在映射矩阵块映射中，输出信号响应于所述映射输入信号而生成，并且映射从多个可选择源单元中出现的错误导出的映射控制信号。施加映射输入信号中的至少一个用于多个源单元的映射输出信号的基本上同时的生成。

3. 发明授权

US08954363B2 Digital-to-analogue converter and neuromorphic circuit using such a converter 有权
标题翻译：使用这种转换器的数模转换器和神经形态电路
公开(公告)号：US08954363B2
公开(公告)日：2015-02-10
申请号：US13705031
申请日：2012-12-04
申请人： Commissariat a l'Energie Atomique et aux Energies Alternatives
发明人： Rodolphe Heliot , Xavier Jehl , Marc Sanquer , Romain Wacquez
IPC分类号： G06N3/04 , H03M1/06 , H03M1/10 , G06N3/02 , H03M1/80 , G06N3/063 , H03M1/74
CPC分类号： G06N3/02 , G06N3/0635 , H03M1/0653 , H03M1/1042 , H03M1/747 , H03M1/80
摘要： A digital-to-analogue converter, with application to electronic circuits with neuromorphic architecture, comprises: transistors of identical nominal geometrical characteristics, but of dispersed current-voltage characteristics, wherein when a constant gate-source voltage is applied to the different transistors, a current varying as a function of the dispersion circulates in the transistor; a digital table receiving a digital word and having a selection output selecting, as a function of the word to be converted, a transistor or transistors supplying a current of desired value representing this word in analogue form. The look-up table is loaded as a function of real measured current-voltage characteristics of different transistors of the set, to establish a look-up between words and current values. The wide variability of characteristics of the transistors, notably their leakage current for a gate-source voltage below the switch-on threshold, allows finding combinations of leakage currents which are a good representation of words to be converted.
摘要翻译：应用于具有神经形态结构的电子电路的数模转换器包括：具有相同标称几何特性但具有分散的电流 - 电压特性的晶体管，其中当恒定的栅极 - 源极电压施加到不同的晶体管时，作为色散的函数的电流随晶体管循环而变化; 接收数字字并且具有选择输出的数字表作为要转换的字的函数，以模拟形式提供表示该字的期望值的电流的晶体管或晶体管。查找表作为集合中不同晶体管的实际测量电流 - 电压特性的函数加载，以建立词和当前值之间的查找。晶体管的特性的广泛变化，特别是其栅极 - 源极电压的低于开启阈值的泄漏电流，允许找到泄漏电流的组合，这是要转换的字的良好表示。

4. 发明申请

US20030227402A1 Method and apparatus for reducing systematic errors in a current steering digital-to-analog converter 审中-公开
标题翻译：用于减少电流转向数模转换器中的系统误差的方法和装置
公开(公告)号：US20030227402A1
公开(公告)日：2003-12-11
申请号：US10395690
申请日：2003-03-24
申请人： Sarnoff Corporation
发明人： Janusz Starzyk , Tom Senko , Russell Mohn
IPC分类号： H03M001/66
CPC分类号： H03M1/0653 , H03M1/685 , H03M1/747
摘要： Method and apparatus for reducing systematic errors in a current steering digital-to-analog converter. The present invention is an efficient method of determining a switching order such that given a known distribution of mismatch errors, the cumulated error is minimized at each DAC code.
摘要翻译：用于减少电流转向数模转换器中的系统误差的方法和装置。本发明是确定开关顺序的有效方法，使得给定已知的失配误差分布，累积误差在每个DAC代码处被最小化。

5. 发明申请

US20120161993A1 DIGITAL ANALOG CONVERTER AND METHOD FOR CALIBRATING CURRENT SOURCES THEREOF 失效
标题翻译：数字模拟转换器及其电流源的校准方法
公开(公告)号：US20120161993A1
公开(公告)日：2012-06-28
申请号：US13312449
申请日：2011-12-06
申请人： Jang Hong CHOI , Hyun Kyu Yu
发明人： Jang Hong CHOI , Hyun Kyu Yu
IPC分类号： H03M1/10
CPC分类号： H03M1/0653 , H03M1/685 , H03M1/747
摘要： Provided is a digital analog converter that output currents having different magnitudes for a digital input value according to a mapping table. The digital analog converter includes: a plurality of current sources; and a calibration unit configured to sort index values for identifying the plurality of current sources according to current magnitudes of the current sources, couple each two current sources which are symmetrical left and right about the center of the sorted index values, and map the current source pairs into a mapping table.
摘要翻译：提供了一种数字模拟转换器，其根据映射表输出对数字输入值具有不同幅度的电流。数字模拟转换器包括：多个电流源; 以及校准单元，被配置为根据当前源的当前幅度对用于识别多个电流源的索引值进行排序，将关于分选的索引值的中心的左右对称的两个电流源耦合，并且将当前源成对映射表。

6. 发明申请

US20120110832A1 CONFIGURATION METHOD AND DEVICE FOR ELECTRICAL AND/OR ELECTRONIC CIRCUITS 有权
标题翻译：电气和/或电子电路的配置方法和装置
公开(公告)号：US20120110832A1
公开(公告)日：2012-05-10
申请号：US13279783
申请日：2011-10-24
申请人： Dominique Morche
发明人： Dominique Morche
IPC分类号： G01R31/28
CPC分类号： H03M1/0653 , H03M1/12 , H03M1/66 , Y10T29/49004
摘要： A method for configuring an electrical circuit comprising several functional blocks having characteristic quantities of the same type and the values whereof are mutually proportional, the functional blocks being built by means of at least one set of electrical elements of a similar type and means for connecting said electrical elements to one another and/or to the rest of the electrical circuit according to different connection configurations, comprising the steps consisting of: measuring a value of a parameter of the electrical circuit for each of a set of connection configurations tested, selection, from among the coupling configurations tested, of one configuration for which the value of the measured parameter corresponds to the case where the mismatch between the values of the characteristic quantities of at least one pair of functional blocks is the smallest, and positioning the connecting means according to the configuration selected.
摘要翻译：一种用于配置电路的方法，该电路包括具有相同类型的特征量的数个功能块及其值相互成比例的功能块，所述功能块通过至少一组类似类型的电气元件构成，以及用于连接所述电气元件根据不同的连接配置彼此和/或电路的其余部分组成，包括以下步骤：测量所测试的一组连接配置中的每一个的电路的参数值，从在测试的耦合配置中，测量参数的值对应于至少一对功能块的特征量的值之间的不匹配最小的情况，并且根据选择配置。

7. 发明授权

US08217819B2 Multiplying DAC and a method thereof 有权
标题翻译：乘法DAC及其方法
公开(公告)号：US08217819B2
公开(公告)日：2012-07-10
申请号：US12941510
申请日：2010-11-08
申请人： Soon-Jyh Chang , Jin-Fu Lin
发明人： Soon-Jyh Chang , Jin-Fu Lin
IPC分类号： H03M1/66
CPC分类号： H03M1/0653 , H03M1/806
摘要： The present invention is directed to a multiplying digital-to-analog converter (MDAC) and its method. First ends of capacitors are electrically coupled to an inverting input node of an amplifier, wherein two of the capacitors are alternatively configured as a feedback capacitor. Each capacitor is composed of at least two sub-capacitors. Second ends of capacitors are electrically coupled to an input signal via a number of sampling switches, and the second ends of the capacitors are electrically coupled to DAC voltages respectively via a number of amplifying switches. A sorting circuit is configured to sort the sub-capacitors, wherein the sorted sub-capacitors are then paired in a manner such that variance of mismatch among the sub-capacitors is thus averaged.
摘要翻译：本发明涉及一种乘法数模转换器（MDAC）及其方法。电容器的第一端电耦合到放大器的反相输入节点，其中两个电容器被配置为反馈电容器。每个电容器由至少两个子电容器组成。电容器的第二端通过多个采样开关电耦合到输入信号，并且电容器的第二端分别经由多个放大开关电耦合到DAC电压。排序电路被配置为对子电容器进行排序，其中分选的子电容器然后被配对，使得子电容器之间的失配的变化被平均化。

8. 发明申请

US20070222653A1 Error Reduction in a Digital-to-Analog (Dac) Converter 有权
标题翻译：数字模拟（Dac）转换器中的误差减少
公开(公告)号：US20070222653A1
公开(公告)日：2007-09-27
申请号：US11587105
申请日：2005-04-11
申请人： Joseph Briaire
发明人： Joseph Briaire
IPC分类号： H03M1/06
CPC分类号： H03M1/0653 , H03M1/742
摘要： In a method to improve error reduction in a digital-to-analog converter (DAC), comprising a mapping matrix block and a plurality of selectable source units which supply signals that in combination provide for analog output signals, mapping input signals, obtained from digital input signals to be converted into the analog output signals, are supplied to the mapping matrix block. In the mapping matrix block mapping output signals are generated in response to said mapping input signals and to mapping control signals derived from errors occurring in the plurality of selectable source units. At least one of the mapping input signals is applied for the substantially simultaneous generation of the mapping output signals for a number of source units.
摘要翻译：在一种用于改善数模转换器（DAC）中的误差减小的方法中，包括映射矩阵块和多个可选择的源单元，其提供组合提供模拟输出信号的信号，映射从数字要转换为模拟输出信号的输入信号，被提供给映射矩阵块。在映射矩阵块映射中，输出信号响应于所述映射输入信号而生成，并且映射从多个可选择源单元中出现的错误导出的映射控制信号。施加映射输入信号中的至少一个用于多个源单元的映射输出信号的基本上同时的生成。

9. 发明授权

US06888487B2 Method of generating a switching sequence for an unary array of conducting branches and a relative thermometrically decoded digital-to-analog converter 有权
标题翻译：产生用于一对导电分支阵列的切换序列的方法和相对温度解析的数模转换器
公开(公告)号：US06888487B2
公开(公告)日：2005-05-03
申请号：US10820427
申请日：2004-04-07
申请人： Francesco Cretti , Fleana Albertoni
发明人： Francesco Cretti , Fleana Albertoni
IPC分类号： H03M1/06 , H03M1/66 , H03M1/68
CPC分类号： H03M1/0653 , H03M1/685
摘要： A method for determining switching sequences of two-dimensional unary arrays of conducting branches of thermometrically decoded D/A converters, in a way that will ensure that the relative INL error function be contained between pre-established symmetrical upper and lower bound functions, has been found. When these upper and lower bound functions are constant, the obtained switching sequence compensates both the linear and the quadratic component of the error distribution and therefore is affected by a very small absolute INL error, which depends essentially on the random component of the error distribution.This method may be easily implemented by a computer program and allows the realization of thermometrically decoded D/A converters affected by a known limited INL error function.
摘要翻译：一种用于确定温差解码的D / A转换器的导通分支的二维一维阵列的切换序列的方法，其方式将确保相对INL误差函数包含在预先建立的对称的上限和下限函数之间，已经被发现。当这些上限和下限函数是常数时，所获得的切换序列补偿误差分布的线性和二次分量，因此受非常小的绝对INL误差的影响，绝对误差主要取决于误差分布的随机分量。该方法可以容易地由计算机程序实现，并且允许实现受已知的有限INL误差函数影响的温差解码的D / A转换器。

10. 发明公开

US20240146322A1 DIGITAL NOISE COUPLING CIRCUIT AND CONTINUOUS TIME MODULATOR INCLUDING THE SAME 审中-公开
公开(公告)号：US20240146322A1
公开(公告)日：2024-05-02
申请号：US18366493
申请日：2023-08-07
申请人： Samsung Electronics Co., Ltd. , Korea Advanced Institute of Science and Technology
发明人： Seong Joong KIM , Seung Tak RYU , Kent Edrian LOZADA
IPC分类号： H03M1/06
CPC分类号： H03M1/0653 , H03M1/0626 , H03M1/0668
摘要： A digital noise coupling circuit includes: an analog-to-digital converter (ADC) configured to convert a quantization error, generated in a process of converting a first analog signal into a first digital signal, into a first digital error signal; a delay cell comprising delay elements configured to delay a transmission of the first digital error signal based on a clock signal; and a digital-to-analog (DA) conversion circuit configured to perform, in an analog domain, noise shaping on the first digital error signal that is delayed and transmitted from the delay cell.

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