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1. 发明申请

US20180102785A1 DIGITAL-TO-ANALOG CONVERTER AND SOURCE DRIVER USING THE SAME 审中-公开
公开(公告)号：US20180102785A1
公开(公告)日：2018-04-12
申请号：US15816197
申请日：2017-11-17
申请人： Innoaxis Co., Ltd
发明人： Hwi-Cheol KIM
IPC分类号： H03M1/66 , G09G3/20 , H03M7/30 , H03M1/74 , H03M1/78 , H03M1/00
CPC分类号： H03M1/66 , G09G3/2007 , G09G2310/027 , G09G2320/0276 , H03M1/00 , H03M1/747 , H03M1/76 , H03M1/785 , H03M7/30
摘要： A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

2. 发明授权

US09866234B1 Digital-to-analog converter 有权
公开(公告)号：US09866234B1
公开(公告)日：2018-01-09
申请号：US15589684
申请日：2017-05-08
申请人： QUALCOMM Incorporated
发明人： Yi-Hung Tseng
IPC分类号： H03M1/66 , H03M1/06 , G06F1/10 , H03M1/74 , H03K5/24 , H03M1/00 , H03K19/003
CPC分类号： H03M1/0678 , G06F1/10 , H03K5/2481 , H03K19/00315 , H03K19/00361 , H03M1/00 , H03M1/742 , H03M1/745 , H03M1/747
摘要： Certain aspects of the present disclosure provide digital-to-analog converters (DACs). One example DAC generally includes a first transistor configured to selectively couple a power source to a load. In a first mode of operation of the DAC, the first transistor is closed and couples the load to the power source. In a second mode of operation of the DAC, the first transistor is open and decouples the load from the power source. The DAC further includes a current limiting circuit selectively coupled between the first transistor and a reference voltage. In the first mode, the current limiting circuit is decoupled from the reference voltage. In the second mode, the current limiting circuit is coupled to the reference voltage.

3. 发明授权

US09859855B2 Class-D amplifiers and methods 有权
公开(公告)号：US09859855B2
公开(公告)日：2018-01-02
申请号：US15079256
申请日：2016-03-24
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Martin Kinyua , Eric Soenen
IPC分类号： H03F3/38 , H03F3/217 , H03F3/183 , H03M1/12 , H03M3/00 , H02M1/12 , H03M1/74
CPC分类号： H03F3/2178 , H02M1/12 , H03F3/183 , H03F3/2175 , H03F2200/03 , H03F2200/135 , H03F2200/165 , H03M1/12 , H03M1/747 , H03M3/434 , H03M3/454 , H03M3/458
摘要： A Class-D amplifier includes an analog-to-digital converter (ADC) having a first input node. The ADC receives a first analog input signal and a first feedback signal at the first input node and generates a first digital signal based on the first analog input signal and the first feedback signal. A digital filter generates a second digital signal based on the first digital signal. An output circuit includes a first output node, the output circuit being configured to generate a first output signal at the first output node based on the second digital signal. A first feedback unit generates the first feedback signal as the first output signal scaled by a gain factor having a constant value in the Z-domain.

4. 发明授权

US09621181B2 Digital to analog converter with output impedance compensation 有权
公开(公告)号：US09621181B2
公开(公告)日：2017-04-11
申请号：US14676227
申请日：2015-04-01
申请人： NATIONAL CHENG KUNG UNIVERSITY
发明人： Tai-Haur Kuo , Hung-Yi Huang , Wei-Cheng Hong
IPC分类号： H03M1/06 , H03M1/80 , H03M1/66
CPC分类号： H03M1/808 , H03M1/0602 , H03M1/0612 , H03M1/664 , H03M1/747
摘要： A digital to analog converter with output impedance compensation has an encoding unit, a current cell array, a summing unit and a compensation unit. The compensation unit is connected to output terminals of the DAC and provides a nonlinear impedance to compensate an original output impedance of the DAC. With the compensated output impedance, the SFDR performance and the linearity of the DAC are improved to obtain a superior input-to-output transfer curve.

5. 发明授权

US09571120B2 Digital to analog converter circuits, apparatus and method for generating a high frequency transmission signal and methods of digital to analog conversion 有权
标题翻译：数模转换器电路，用于产生高频传输信号的装置和方法以及数模转换的方法
公开(公告)号：US09571120B2
公开(公告)日：2017-02-14
申请号：US14835031
申请日：2015-08-25
申请人： Intel IP Corporation
发明人： Franz Kuttner , Antonio Passamani , Davide Ponton
IPC分类号： H03M1/66 , H03M1/74 , H03M1/00 , H03M1/12 , H03M3/00
CPC分类号： H03M1/662 , H03M1/00 , H03M1/12 , H03M1/74 , H03M1/747 , H03M3/30
摘要： A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.
摘要翻译：数模转换器电路包括多个数模转换器单元。数模转换器电路还包括控制电路，其被配置为基于数字信号的第一相位分量来控制多个数模转换器单元中的数模转换器单元的操作，该数字信号包括将在第一时间间隔，并且基于数字信号的第二相位分量，包括将在第二时间间隔期间发送的信息。

6. 发明授权

US09571117B2 Digital-analog conversion apparatus and method 有权
标题翻译：数模转换装置及方法
公开(公告)号：US09571117B2
公开(公告)日：2017-02-14
申请号：US14311812
申请日：2014-06-23
申请人： Samsung Electronics Co., Ltd.
发明人： Jong-Woo Lee
IPC分类号： H03M1/66 , H03M1/10 , H03M1/68 , G06F11/07 , H03M1/06 , H03M1/74
CPC分类号： H03M1/1071 , G06F11/0751 , H03M1/0651 , H03M1/1019 , H03M1/66 , H03M1/682 , H03M1/687 , H03M1/747
摘要： An apparatus and a method for digital-analog conversion are provided. The apparatus includes a first cell matrix for outputting a current of a signal corresponding to a number of Most Significant Bits (MSBs) of an input digital signal, a second cell matrix for outputting a current of a signal corresponding to a number of Least Significant Bits (LSBs) of the input digital signal, an amplifier for amplifying the output current of the second cell matrix at a preset amplification, and an adder for adding the output current of the first cell matrix and the output current of the amplifier.
摘要翻译：提供了一种用于数模转换的装置和方法。该装置包括用于输出与输入数字信号的最高有效位数（MSB）相对应的信号的电流的第一单元矩阵，用于输出与多个最低有效位相对应的信号的电流的第二单元矩阵（LSB），用于以预设放大放大第二单元矩阵的输出电流的放大器，以及用于将第一单元矩阵的输出电流和放大器的输出电流相加的加法器。

7. 发明申请

US20160359496A1 Apparatus for Offset Trimming and Associated Methods 有权
标题翻译：偏移修整和相关方法的设备
公开(公告)号：US20160359496A1
公开(公告)日：2016-12-08
申请号：US14732702
申请日：2015-06-06
申请人： Silicon Laboratories Inc.
发明人： Axel Thomsen , Alan L. Westwick , Ricky Setiawan , Rex Wong Tak Ying
IPC分类号： H03M1/06 , H03M1/66 , H03M1/00 , H03K5/003
CPC分类号： H03M1/0607 , H03K5/003 , H03M1/00 , H03M1/002 , H03M1/0609 , H03M1/66 , H03M1/664 , H03M1/682 , H03M1/747 , H03M1/808
摘要： Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit, which includes a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. The output offset of the first circuit is trimmed by adding the second current to the first current.
摘要翻译：公开了用于增益和偏移修整的装置和相关方法。在一个示例性实施例中，一种装置包括第一电路，其包括产生第一电流的第一跨导级。第一个电路具有输出偏移。该装置还包括偏移调整电路，其包括提供从多个电压值可选择的输出电压的第二电路和第二跨导级，以响应于第二电路的输出电压产生第二电流。通过将第二电流加到第一电流来修整第一电路的输出偏移。

8. 发明申请

US20160359495A1 APPARATUS FOR GAIN SELECTION WITH COMPENSATION FOR PARASITIC ELEMENTS AND ASSOCIATED METHODS 有权
标题翻译：用于增益选择的装置用于PARASITICELEMENTS和相关方法的补偿
公开(公告)号：US20160359495A1
公开(公告)日：2016-12-08
申请号：US14732701
申请日：2015-06-06
申请人： Silicon Laboratories Inc.
发明人： Axel Thomsen , Alan L. Westwick , Ricky Setiawan , Rex Wong Tak Ying
IPC分类号： H03M1/06 , H03M1/00 , H03M1/66 , H03K5/003
CPC分类号： H03M1/0607 , H03K5/003 , H03M1/00 , H03M1/002 , H03M1/0609 , H03M1/66 , H03M1/664 , H03M1/682 , H03M1/747 , H03M1/808
摘要： Apparatus and associated methods are disclosed for gain programming or selection with parasitic element compensation. In one exemplary embodiment, an apparatus includes a first circuit that has a first programmable gain, and includes a first set of components having parasitic elements. The apparatus also includes a second circuit that has a second programmable gain, and includes a second set of components having parasitic elements. The apparatus has a gain that is a product of the first and second programmable gains. A gain error because of the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.
摘要翻译：公开了用于利用寄生元件补偿进行增益编程或选择的装置和相关方法。在一个示例性实施例中，装置包括具有第一可编程增益的第一电路，并且包括具有寄生元件的第一组分量。该装置还包括具有第二可编程增益的第二电路，并且包括具有寄生元件的第二组分量。该装置具有作为第一和第二可编程增益的乘积的增益。通过将第一可编程增益设置为第二可编程增益的倒数来消除由于第一和第二组分组的寄生元件引起的增益误差。

9. 发明授权

US09503113B1 Apparatus for offset trimming and associated methods 有权
标题翻译：偏移修整装置及相关方法
公开(公告)号：US09503113B1
公开(公告)日：2016-11-22
申请号：US14732702
申请日：2015-06-06
申请人： Silicon Laboratories Inc.
发明人： Axel Thomsen , Alan L. Westwick , Ricky Setiawan , Rex Wong Tak Ying
IPC分类号： H03M1/06 , H03K5/003 , H03M1/66 , H03M1/00 , H03M1/74
CPC分类号： H03M1/0607 , H03K5/003 , H03M1/00 , H03M1/002 , H03M1/0609 , H03M1/66 , H03M1/664 , H03M1/682 , H03M1/747 , H03M1/808
摘要： Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit, which includes a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. The output offset of the first circuit is trimmed by adding the second current to the first current.
摘要翻译：公开了用于增益和偏移修整的装置和相关方法。在一个示例性实施例中，一种装置包括第一电路，其包括产生第一电流的第一跨导级。第一个电路具有输出偏移。该装置还包括偏移调整电路，其包括提供从多个电压值可选择的输出电压的第二电路和第二跨导级，以响应于第二电路的输出电压而产生第二电流。通过将第二电流加到第一电流来修整第一电路的输出偏移。

10. 发明授权

US09490774B2 Channel select filter apparatus and method 有权
公开(公告)号：US09490774B2
公开(公告)日：2016-11-08
申请号：US14619940
申请日：2015-02-11
申请人： ESS Technology, Inc.
发明人： A. Martin Mallinson
IPC分类号： G06G7/16 , H03H17/02 , H03H15/00 , H03M1/68 , H03M1/74 , B60N2/00
CPC分类号： H03H17/0248 , B60N2/002 , H03H15/00 , H03M1/687 , H03M1/745 , H03M1/747
摘要： Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non-radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein. Another circuit implements a multiplying element and digital-to-analog converter with selective enablement of duplicate current source devices. Another circuit implements a multiplying element and digital-to-analog converter with variable effective length of the digital-to-analog converter. In one such circuit one or more current sources of a multiplier element are deselected to remove a noise contribution of the multiplier element, as described herein. A complex filter circuit includes a pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a common resistor network to perform weighted addition. One such circuit further includes a second pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a second common resistor network to perform weighted addition.

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