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1. 发明申请

US20190197259A1 METHOD FOR DETERMINING AN INTEGRITY SUM, ASSOCIATED COMPUTER PROGRAM AND ELECTRONIC ENTITY 审中-公开
公开(公告)号：US20190197259A1
公开(公告)日：2019-06-27
申请号：US16193311
申请日：2018-11-16
申请人： IDEMIA France
发明人： Luk BETTALE , Nicolas DEBANDE , Aurélien GREUET
IPC分类号： G06F21/64 , H03M13/09 , G06F21/60 , H04L9/06
CPC分类号： G06F21/64 , G06F11/1004 , G06F21/602 , H03M13/096 , H04L9/002 , H04L9/0637 , H04L2209/046
摘要： A method for determining a first integrity sum including the following steps: determining a first masked item of data by application of an “exclusive OR” operation between a first item of data and a first data mask; —determining a second item of data by application to the first masked item of data of a first cryptographic function, the second item of data being masked by a second data mask; —determining a second integrity sum associated with the second item of data by application to the second item of data of a checksum function; and determining the first integrity sum by application of an “exclusive OR” operation between the second integrity sum and a third integrity sum associated with the second data mask. A computer program and an electronic entity are also described.

2. 发明授权

US09891985B1 256-bit parallel parser and checksum circuit with 1-hot state information bus 有权
公开(公告)号：US09891985B1
公开(公告)日：2018-02-13
申请号：US14929275
申请日：2015-10-31
申请人： Netronome Systems, Inc.
发明人： Joseph M. Lamb , Benjamin D. Findlen
IPC分类号： G06F11/10 , H03M13/09
CPC分类号： G06F11/1004 , H03M13/096
摘要： A parser and checksum circuit includes a 256-bit data bus, IPV4, IPV6, TCP, and UDP state signal buses, a checksum summer and compare circuit, four 64-bit parsing circuits, a V6 extension processor, and a parse state context circuit. Each of the 64-bit parsing circuits includes two 32-bit parsing circuits. The data bus receives a data signal that is part of a packet. IPV4, IPV6, TCP, and UDP state signals are each configurable into 1-hot states where at most 1-bit is digital logic high. Each of the 1-hot states corresponds to a segment of a packet header of one of the IPV4, IPV6, TCP, and UDP protocols. Each 32-bit parsing circuit receives a 1-bit shifted version of the state signals received by the adjacent 32-bit parsing circuit and receives a portion of the data signal. State signals and the data signal portion are received in parallel during a single clock cycle.

3. 发明授权

US09866338B2 Encoding and decoding method for short-range communication using an acoustic communication channel 有权
公开(公告)号：US09866338B2
公开(公告)日：2018-01-09
申请号：US14267463
申请日：2014-05-01
申请人： Samsung Electronics Co., Ltd.
发明人： Hee-Won Jung , Seung-Gun Park , Gi-Sang Lee , Jun-Ho Koh , Sang-Mook Lee , Sergey Zhidkov
IPC分类号： H04J3/04 , H04J3/24 , H04L1/00 , H03M13/09 , H03M13/15 , H03M13/27 , H03M13/29 , H03M13/00
CPC分类号： H04J3/04 , H03M13/09 , H03M13/096 , H03M13/15 , H03M13/27 , H03M13/2936 , H03M13/2957 , H03M13/6356 , H04J3/24 , H04L1/0041 , H04L1/007
摘要： Encoding and decoding methods are provided. An information object is encoded according to a preset encoding scheme. A preset set of bits is selected from the encoded information object and the selected set of bits is output as a sample. A control packet including information on a sample number is generated. The sample is assembled with the control packet. The sample is modulated into a sound signal according to a preset scheme. An input sound signal is demodulated according to the preset scheme. Sample bits and control packet bits containing information of the sample are separated from each other in demodulated received bits. Address information corresponding to each bit of the sample is generated according to the control packet. A soft decision of the sample bits is summed for each piece of the generated address information. A sample decoding of the summed soft decision of the sample bits is performed.

4. 发明授权

US09678828B2 Error detection capability over CCIe protocol 有权
公开(公告)号：US09678828B2
公开(公告)日：2017-06-13
申请号：US14511160
申请日：2014-10-09
申请人： QUALCOMM Incorporated
发明人： Shoichiro Sengoku
IPC分类号： G06F11/10 , G06F13/42 , H03M13/09
CPC分类号： G06F11/1004 , G06F13/4221 , H03M13/096
摘要： A device is provided comprising a shared bus, a slave device, and a master device. The slave device may be coupled to the shared bus. The master device may be coupled to the control data bus and adapted to manage communications on the shared bus. Transmissions over the shared bus are a plurality of bits that are encoded into ternary numbers which are then transcoded into symbols for transmission, and either the 3 least significant bits or the least significant in the plurality of bits are used for error detection of the transmission.

5. 发明申请

US20160188395A1 ROBUST SERDES WRAPPER 有权
标题翻译：坚固的SERDES WRAPPER
公开(公告)号：US20160188395A1
公开(公告)日：2016-06-30
申请号：US14812871
申请日：2015-07-29
申请人： SEAKR ENGINEERING, INC.
发明人： ERIK BUEHLER
IPC分类号： G06F11/07
CPC分类号： G06F11/079 , G06F11/0706 , G06F11/0751 , H03M9/00 , H03M13/03 , H03M13/096 , H03M13/098 , H04L1/0022 , H04L1/0045 , H04L1/0061 , H04L1/16 , H04L1/22 , H04L2001/0096
摘要： Light-weight, configurable error detection in a satellite communication system that detects invalid SerDes lanes via hash codes appended to packets of data in the lanes. An indication can be passed back upstream about the invalid lane so that the lane can be reset. Error correction can be provided by reconstructing the bit data in the invalid SerDes lane based on parity information in an optional parity lane.
摘要翻译：卫星通信系统中的重量轻，可配置的错误检测，通过附加到车道数据包的散列码来检测无效的SerDes车道。可以向上游传递关于无效车道的指示，使得可以重置车道。可以通过基于可选奇偶校验通道中的奇偶校验信息重建无效SerDes通道中的位数据来提供纠错。

6. 发明申请

US20160139988A1 MEMORY UNIT 审中-公开
标题翻译：记忆单元
公开(公告)号：US20160139988A1
公开(公告)日：2016-05-19
申请号：US14898539
申请日：2013-07-31
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： Naveen Muralimanohar , Erik Ordentlich
IPC分类号： G06F11/10 , G06F3/06
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/0644 , G06F3/0683 , G06F11/1004 , G06F11/108 , H03M13/09 , H03M13/096 , H03M13/1515 , H03M13/152 , H03M13/2906
摘要： Operating a memory unit during a memory access operation. The memory unit includes a configuration of N data chips. A line of data stored in the memory unit is divided, with a controller, into a first portion and a second portion. The first portion of the line of data is encoded, with an outer code encoder, to generate an outer code output. The second portion of the line of data and the outer code output from the outer code encoder are encoded, with an inner code encoder, to generate an inner code output. A first layer of protection for the line of data is generated based on the inner code output and is stored to the memory unit, where the first layer of protection includes local error detection (LED) information combined with the line of data. A second layer of protection for the line of data is generated based on the first layer of protection and is stored to the memory unit. A decoding operation to retrieve the line of data is performing at the controller.
摘要翻译：在存储器访问操作期间操作存储器单元。存储单元包括N个数据芯片的配置。存储在存储器单元中的数据线与控制器分成第一部分和第二部分。数据行的第一部分使用外部代码编码器进行编码，以生成外部代码输出。数据行的第二部分和从外码编码器输出的外码用内码编码器编码，以产生内码输出。基于内部代码输出产生用于数据线的第一层保护，并将其存储到存储单元中，其中第一层保护包括与数据行组合的本地错误检测（LED）信息。基于第一层保护来生成数据线的第二层保护层，并将其存储到存储器单元中。在控制器执行用于检索数据行的解码操作。

7. 发明申请

US20160118999A1 Fast Update of Data Packet Checksums 有权
标题翻译：快速更新数据包校验和
公开(公告)号：US20160118999A1
公开(公告)日：2016-04-28
申请号：US14521035
申请日：2014-10-22
申请人： Dell Products, LP
发明人： George Weigt
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H03M13/096 , G06F11/1004 , H03M13/07 , H03M13/093 , H04L1/0061 , H04L1/0072 , H04L1/0083 , H04L69/16 , H04L69/161
摘要： A device includes a processor and a checksum module, wherein the checksum module calculates, for first data, an updated checksum that complies with Internet Engineering Task Force Request For Comments Number 1624 using twos-complement arithmetic. The processor replaces the original checksum with the updated checksum to update a data packet.
摘要翻译：设备包括处理器和校验和模块，其中校验和模块针对第一数据计算使用二进制补码运算符合因特网工程任务组对注释号1624的请求的更新校验和。处理器用更新的校验和替换原始校验和，以更新数据包。

8. 发明授权

US09300324B2 CRC counter normalization 有权
公开(公告)号：US09300324B2
公开(公告)日：2016-03-29
申请号：US14638889
申请日：2015-03-04
申请人： TQ DELTA, LLC
发明人： Marcos C. Tzannes
IPC分类号： H03M13/00 , H03M13/09 , H04L1/00 , G06F11/10
CPC分类号： G06F11/1004 , H03M13/09 , H03M13/096 , H04L1/0045 , H04L1/0061
摘要： The ability to accurately and efficiently calculate and report communication errors is becoming more important than ever in today's communications environment. More specifically calculating and reporting CRC anomalies in a consistent manner across a plurality of communications connections in a network is crucial to accurate error reporting. Through a normalization technique applied to a CRC computation period (e.g., the PERp value), accurate error identification and reporting for each individual connection can be achieved.

9. 发明申请

US20160055053A1 METHODS AND APPARATUSES UTILIZING CHECK BIT DATA GENERATION 有权
标题翻译：使用检查位数据生成的方法和设备
公开(公告)号：US20160055053A1
公开(公告)日：2016-02-25
申请号：US14467983
申请日：2014-08-25
申请人： Seagate Technology LLC
发明人： Jon D. Trantham , Brian T. Edgar , Mark Gaertner , Bruce Buch
IPC分类号： G06F11/10 , H03M13/09
CPC分类号： G06F11/1004 , G06F11/1012 , H03M13/09 , H03M13/096
摘要： Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit.
摘要翻译：本公开的某些示例性方面涉及其中逻辑电路基于从主机接收的用户数据生成错误检测码的方法和装置，并进一步产生要写入非易失性存储器的第一组校验位通过将错误检测码与用户数据的散列数据地址组合在一起，与用户数据相结合。在一些实施例中，与用户数据相关联的校验位提供用户数据被写入非易失性存储器电路的适当物理块地址中的验证。

10. 发明授权

US09262159B2 Performing a cyclic redundancy checksum operation responsive to a user-level instruction 有权
公开(公告)号：US09262159B2
公开(公告)日：2016-02-16
申请号：US14579538
申请日：2014-12-22
申请人： Intel Corporation
发明人： Steven R. King , Frank L. Berry , Mlchael E. Kounavis
IPC分类号： H03M13/09 , G06F9/30 , G06F11/10 , G06F15/76 , H03M13/00 , G06T1/20
CPC分类号： G06F11/1004 , G06F9/30003 , G06F9/30018 , G06F9/30032 , G06F15/76 , G06T1/20 , H03M13/00 , H03M13/09 , H03M13/093 , H03M13/096 , H03M13/157
摘要： In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

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