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1. 发明授权

US09954546B2 Removal of sampling clock jitter induced in an output signal of an analog-to-digital converter 有权
公开(公告)号：US09954546B2
公开(公告)日：2018-04-24
申请号：US15603713
申请日：2017-05-24
申请人： Advantest Corporation
发明人： Bernd Laquai
IPC分类号： H03M1/08 , H03M1/10
CPC分类号： H03M1/0836 , H03M1/1071 , H03M1/1085 , H03M1/12
摘要： An automated test equipment for analyzing an analog time domain output signal of an electronic device under test includes: an analog-to-digital converter configured for converting an analog time domain signal; a sampling clock configured for producing a clock signal; a time-to-frequency converter configured for converting the digital time domain signal into a digital frequency domain signal so that the digital frequency domain signal is represented by frequency bins; a memory device configured for storing a set of empirically determined operating parameters; and a jitter components removal module for removing jitter components produced by the analog-to-digital converter, wherein the jitter removal module is configured for subtracting the lower spur and the upper spur of each frequency bin of the frequency bins from the digital frequency domain signal so that the cleaned digital frequency domain signal is produced.

2. 发明申请

US20180097525A1 ANALOG-TO-DIGITAL CONVERTER NON-LINEARITY CORRECTION USING COEFFICIENT TRANSFORMATION 有权
公开(公告)号：US20180097525A1
公开(公告)日：2018-04-05
申请号：US15674175
申请日：2017-08-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Jawaharlal TANGUDU , Chandrasekhar SRIRAM
IPC分类号： H03M1/08
CPC分类号： H03M1/08 , H03M1/06 , H03M1/0836 , H03M1/0854 , H03M1/1042
摘要： Circuitry for correcting non-linearity of an analog-to-digital converter. A non-linearity correction system for an analog-to-digital converter (ADC) includes coefficient storage, coefficient transformation circuitry, and correction circuitry. The coefficient storage is encoded with a first set of coefficients for correcting non-linearity of the ADC at a first sampling rate. The coefficient transformation circuitry is coupled to the coefficient storage. The coefficient transformation circuitry is configured to generate a second set of coefficients for correcting non-linearity of the ADC at a different sampling rate. The correction circuitry is configured to apply the second set of coefficients to correct non-linearity in output of the ADC while the ADC is operating at the different sampling rate.

3. 发明申请

US20180091165A1 INCREMENTAL PRELOADING IN AN ANALOG-TO-DIGITAL CONVERTER 审中-公开
公开(公告)号：US20180091165A1
公开(公告)日：2018-03-29
申请号：US15649313
申请日：2017-07-13
申请人： Analog Devices, Inc.
发明人： Baozhen Chen , Edward C. Guthrie , Michael C.W. Coln , Mark D. Maddox
IPC分类号： H03M1/08
CPC分类号： H03M1/0836 , H03M1/0651 , H03M1/0863 , H03M1/14 , H03M1/466 , H03M1/68 , H03M1/804 , H03M1/806
摘要： During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.

4. 发明授权

US09866230B2 Method and apparatus for calibration of a time interleaved ADC 有权
公开(公告)号：US09866230B2
公开(公告)日：2018-01-09
申请号：US15395390
申请日：2016-12-30
申请人： Entropic Communications LLC.
发明人： Josephus Van Engelen , Aaron Buchwald , Ralph Duncan
IPC分类号： H03M1/06 , H03M1/38 , H03M1/12
CPC分类号： H03M1/38 , H03M1/0675 , H03M1/0678 , H03M1/0836 , H03M1/1215 , H03M1/124 , H03M1/14
摘要： Systems and methods for converting analog signals to digital signals. A reference slice is associated with each of a plurality of active slices to balance the loading on an active sampling track and hold amplifier within each active slice. Alternatively, the reference slice is split into a portion having a reference ADC that is shared by a plurality of partial reference slices, each partial reference slice having a partial reference input module.

5. 发明申请

US20170257107A1 REMOVAL OF SAMPLING CLOCK JITTER INDUCED IN AN OUTPUT SIGNAL OF AN ANALOG-TO-DIGITAL CONVERTER 有权
公开(公告)号：US20170257107A1
公开(公告)日：2017-09-07
申请号：US15603713
申请日：2017-05-24
申请人： Advantest Corporation
发明人： Bernd Laquai
IPC分类号： H03M1/08 , H03M1/10
CPC分类号： H03M1/0836 , H03M1/1071 , H03M1/1085 , H03M1/12
摘要： An automated test equipment for analyzing an analog time domain output signal of an electronic device under test includes: an analog-to-digital converter configured for converting an analog time domain signal; a sampling clock configured for producing a clock signal; a time-to-frequency converter configured for converting the digital time domain signal into a digital frequency domain signal so that the digital frequency domain signal is represented by frequency bins; a memory device configured for storing a set of empirically determined operating parameters; and a jitter components removal module for removing jitter components produced by the analog-to-digital converter, wherein the jitter removal module is configured for subtracting the lower spur and the upper spur of each frequency bin of the frequency bins from the digital frequency domain signal so that the cleaned digital frequency domain signal is produced.

6. 发明申请

US20170141786A1 DIGITAL DOWN CONVERTER WITH EQUALIZATION 有权
公开(公告)号：US20170141786A1
公开(公告)日：2017-05-18
申请号：US15229578
申请日：2016-08-05
申请人： Guzik Technical Enterpises
发明人： Semen P. Volfbeyn , Anatoli B. Stein , Alexander Taratorin
IPC分类号： H03M1/60 , H03M1/08 , H03M1/06
CPC分类号： H03M1/60 , H03D7/165 , H03M1/0626 , H03M1/0836 , H03M1/1215 , H04B1/0014
摘要： A digital down converter with an equalizer translates an ADC output signal to a low frequency spectral region, followed by decimation. All operations of correction of the processed signal are carried out with a reduced sampling rate compared with sampling rates of the prior art. Equalization is performed only in a frequency pass band of the down converter. The achieved reduction of the required computation resources is sufficient to enable the down converter with equalization to operate in a real time mode.

7. 发明申请

US20170134033A1 Interleaved Analog-to-Digital Converter and Method for Calibrating an Interleaved Analog-to-Digital Converter 有权
公开(公告)号：US20170134033A1
公开(公告)日：2017-05-11
申请号：US15319162
申请日：2014-06-30
申请人： Synopsys, Inc.
发明人： Pedro Miguel Ferreira de Figueiredo
IPC分类号： H03M1/10 , H03M1/12
CPC分类号： H03M1/1009 , H03M1/0836 , H03M1/1038 , H03M1/1215
摘要： An interleaved analog-to-digital converter, ADC, comprises a first and a second sub-ADC (ADC1, ADC2) and a timing control unit (TC). The first sub-ADC (ADC1) is configured to convert a first calibration signal (V1cal) into a first calibration code (CC1) depending on a first sub-clock signal (Φ1). The second sub-ADC (ADC2) comprises a programmable delay element (DE2) configured to generate a calibrated second sub-clock signal (Φ2′) by shifting a phase of a second sub-clock signal (Φ2) by a delay depending on a control signal. The second sub-ADC (ADC2) is configured to convert a second calibration signal (V2cal) into a second calibration code (CC2) depending on the calibrated second sub-clock signal (Φ2′). The timing control (TC) unit generates the control signal (CS) comparing the second calibration code (CC2) to the first calibration code (CC1).

8. 发明申请

US20160226509A1 Distributed Combiner for Parallel Discrete-to-Linear Converters 有权
标题翻译：用于并行离散到线性转换器的分布式组合器
公开(公告)号：US20160226509A1
公开(公告)日：2016-08-04
申请号：US14996497
申请日：2016-01-15
申请人： Syntropy Systems, LLC
发明人： Christopher Pagnanelli
IPC分类号： H03M1/66 , H03M3/00 , H03M1/08
CPC分类号： H03M1/661 , H03F3/211 , H03M1/08 , H03M1/0836 , H03M1/662 , H03M3/30 , H03M3/50
摘要： Provided are, among other things, systems, apparatuses methods and techniques for providing a complete output signal from a set of partial signals, which in turn have been generated by parallel processing paths in the time-interleaved and/or frequency-interleaved conversion of discrete signals to linear signals (i.e., discrete-to-linear conversion). One such apparatus includes a distributed network comprising a plurality of ladder networks through which input signals propagate before being combined to form an output signal.
摘要翻译：除其他之外，提供了用于从一组部分信号提供完整的输出信号的系统，装置方法和技术，这些部分信号又在离散的时间交织和/或频率交织的转换中由并行处理路径产生信号到线性信号（即离散到线性转换）。一种这样的设备包括分布式网络，其包括多个梯形网络，输入信号在组合之前通过该梯形网络传播以形成输出信号。

9. 发明申请

US20160191071A1 METHOD AND APPARATUS FOR CALIBRATION OF A TIME INTERLEAVED ADC 有权
标题翻译：用于校准时间间隔ADC的方法和装置
公开(公告)号：US20160191071A1
公开(公告)日：2016-06-30
申请号：US14858793
申请日：2015-09-18
申请人： Luxtera, Inc.
发明人： Josephus Van Engelen , Aaron Buchwald , Ralph Duncan
IPC分类号： H03M1/38 , H03M1/12 , H03M1/06
CPC分类号： H03M1/38 , H03M1/0675 , H03M1/0678 , H03M1/0836 , H03M1/1215 , H03M1/124 , H03M1/14
摘要： A system for calibrating time interleaved ADCs is disclosed and may include a time interleaved analog-to-digital converter (ADC) for converting analog signals to digital signals, the time interleaved ADC comprising: a plurality of active slices, and a plurality of reference slices, each reference slice associated with a corresponding one of the plurality of active slices. An output of each reference slice may be used to correct distortion in an output of the corresponding active slice. Each active slice may sample an input signal at a first rate and each associated reference slice may sample the input signal at a second rate, the second rate being slower than the first rate. Each sample taken by one of the plurality of reference slices may then be taken concurrent with a sample taken by the associated active slice. Each reference slice may include a reference sampling module and a dummy load.
摘要翻译：公开了一种用于校准时间交错ADC的系统，并且可以包括用于将模拟信号转换为数字信号的时间交织模数转换器（ADC），所述时间交织ADC包括：多个活动切片和多个参考切片，每个参考切片与所述多个活动切片中的对应的一个相关联。可以使用每个参考片的输出来校正相应活动片的输出中的失真。每个活动切片可以以第一速率对输入信号进行采样，并且每个相关联的参考切片可以以第二速率对输入信号进行采样，第二速率比第一速率慢。然后可以将多个参考切片中的一个采样的每个采样与由相关联的活动切片采集的采样同时进行。每个参考切片可以包括参考采样模块和虚拟负载。

10. 发明授权

US09369142B2 Multi-channel time-interleaved analog-to-digital converter 有权
标题翻译：多通道时间交错模数转换器
公开(公告)号：US09369142B2
公开(公告)日：2016-06-14
申请号：US14747691
申请日：2015-06-23
申请人： Huawei Technologies Co., Ltd.
发明人： Bingsen Qiu
IPC分类号： H03M1/06 , H03M1/10 , H03M1/12 , H03M1/08
CPC分类号： H03M1/0631 , H03M1/0624 , H03M1/0626 , H03M1/0836 , H03M1/1033 , H03M1/1061 , H03M1/1215
摘要： The present invention provides a multi-channel time-interleaved analog-to-digital converter, including: a clock generation circuit, configured to generate a work clock of the analog-to-digital converter; a channel ADC group, including M ADC channels, and configured to convert, under the control of the clock generation circuit and in a time division multiplexing manner, one high-speed analog input signal into M low-speed digital output signals; a channel mismatch detection circuit, configured to detect in real time timing skew errors of output signals of the M ADC channels; a signal compensation and reconstruction circuit, configured to perform, according to the timing skew parameters detected, compensation and reconstruction on the digital output signals output by the channel ADC group; and a signal combining circuit, configured to combine the M low-speed output signals that are of the channels and generated after the compensation by the signal compensation and reconstruction circuit.
摘要翻译：本发明提供了一种多通道时间交织模数转换器，包括：时钟产生电路，被配置为产生模数转换器的工作时钟; 一个通道ADC组，包括M个ADC通道，并被配置为在时钟发生电路的控制下并且以时分复用方式将一个高速模拟输入信号转换为M个低速数字输出信号; 信道失配检测电路，被配置为实时检测所述M个ADC信道的输出信号的定时偏差误差; 信号补偿和重构电路，被配置为根据检测到的定时偏差参数执行由信道ADC组输出的数字输出信号的补偿和重建; 以及信号组合电路，被配置为组合由信道补偿和重构电路在补偿之后产生的信道的M个低速输出信号。

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