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1. 发明申请

US20190166027A1 Distributed Checksum Calculation for Communication Packets 审中-公开
公开(公告)号：US20190166027A1
公开(公告)日：2019-05-30
申请号：US16045781
申请日：2018-07-26
申请人： Marvell World Trade Ltd.
发明人： Lukas Reinbold , Thomas Kniplitsch
IPC分类号： H04L12/26 , H04L29/06 , H04L12/863
CPC分类号： H04L43/0847 , H04L1/0061 , H04L12/46 , H04L47/6245 , H04L69/08 , H04L69/22 , H04N21/2383 , H04N21/4382
摘要： A packet generator includes a checksum calculator configured to distinguish, in a communication packet belonging to a sequence of packets, between (i) one or more constant values of a header of the packet, the one or more constant values remaining unchanged across the packets in the sequence, (ii) a payload of the packet, and (iii) one or more variable values of the header, the one or more variable values changing among the packets in the sequence, to determine a constant-values partial checksum calculated over the constant values of the header, to calculate a payload partial checksum over the payload, to calculate a final checksum value for the packet based on (i) the constant-values partial checksum, (ii) the payload partial checksum and (iii) the variable values of the header, and to insert the final checksum value into the packet. An egress interface transmits the packet over a network.

2. 发明申请

US20190140963A1 METHODS AND APPARATUS FOR PROVIDING TIMING ANALYSIS FOR PACKET STREAMS OVER PACKET CARRIERS 审中-公开
公开(公告)号：US20190140963A1
公开(公告)日：2019-05-09
申请号：US16231506
申请日：2018-12-22
申请人： Tellabs Opertations, Inc.
发明人： Anthony L. Sasak , Christopher V. O'Brien
IPC分类号： H04L12/841 , H04L12/863 , H04J3/14 , H04J3/06
CPC分类号： H04L47/283 , H04J3/0632 , H04J3/065 , H04J3/14 , H04L41/064 , H04L43/106 , H04L47/621 , H04L47/6245
摘要： A network device such as a router or switch, in one embodiment, includes a timing analyzer which is capable of providing timing analysis over one or more network circuits. The timing analyzer, in one aspect, receives a data packet traveling across a circuit emulation service (“CES”) circuit such as T1 or E1 circuit. Upon obtaining an arrival timestamp associated with the data packet, the arrival timestamp is stored in a timestamp buffer in accordance with a first-in first-out (“FIFO”) storage sequence. After identifying the oldest arrival timestamp in the timestamp buffer, an offset is generated based on the result of comparison between the arrival timestamp and the oldest timestamp. The timing analyzer can also be configured to generate timing reports on-demand based on generated offset(s).

3. 发明申请

US20190089522A1 System for Serializing High Speed Data Signals 审中-公开
公开(公告)号：US20190089522A1
公开(公告)日：2019-03-21
申请号：US16169454
申请日：2018-10-24
申请人： Synopsys, Inc.
发明人： Biman Chattopadhyay , Ravi Mehta
IPC分类号： H04L7/06 , H04J3/06 , H04J3/04 , H04L12/863 , H03M9/00
CPC分类号： H04L7/06 , H03M9/00 , H04J3/047 , H04J3/0685 , H04L47/6245
摘要： A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

4. 发明申请

US20180062987A1 ETHERNET TO SPACEWIRE BRIDGE 审中-公开
公开(公告)号：US20180062987A1
公开(公告)日：2018-03-01
申请号：US15247699
申请日：2016-08-25
申请人： Honeywell International Inc.
发明人： Alvin Badillo , David Jay Kessler , Brett Douglas Oliver , Barry Lawrence Allred
IPC分类号： H04L12/721 , H04L12/805 , H04L29/12 , H04L12/933 , H04L12/863 , H04L12/823 , H04L29/06
CPC分类号： H04L45/66 , H04L12/40006 , H04L12/66 , H04L47/32 , H04L47/36 , H04L47/6245 , H04L49/109 , H04L61/6022 , H04L69/22 , H04L2012/4028
摘要： A system for interfacing Ethernet with SpaceWire comprises a processor including an Ethernet MAC, and a bridge device connected between the processor and a SpaceWire subsystem or network. The bridge device comprises a SpaceWire physical interface that receives SpaceWire data packets, and an Ethernet MAC packet builder that includes digital logic for segmentation of the data packets into Ethernet compatible packet segments. An Ethernet media independent interface receives the packet segments from the packet builder and outputs the packet segments to the Ethernet MAC. The Ethernet media independent interface also receives Ethernet data packets transmitted from the Ethernet MAC. An Ethernet MAC packet extractor receives the Ethernet data packets from the Ethernet media independent interface and includes digital logic for performing reassembly of the Ethernet data packets into SpaceWire compatible data packets, which are sent to the SpaceWire physical interface for transmission to the SpaceWire subsystem or network.

5. 发明申请

US20180034749A1 SYSTEM AND METHOD FOR DISTRIBUTING AND REPLAYING TRIGGER PACKETS VIA A VARIABLE LATENCY BUS INTERCONNECT 审中-公开
公开(公告)号：US20180034749A1
公开(公告)日：2018-02-01
申请号：US15224735
申请日：2016-08-01
申请人： QUALCOMM INCORPORATED
发明人： MARTYN RYAN SHIRLEN
IPC分类号： H04L12/861 , H04L12/863 , H04L12/923 , H04L12/933 , H04L29/06
CPC分类号： H04L49/9057 , G06F11/3075 , G06F11/3476 , G06F2201/835 , G06F2201/86 , H04L47/6245 , H04L47/762 , H04L49/109 , H04L69/28
摘要： Systems and methods are disclosed for distributing and replaying trigger packets via a variable latency bus interconnect in a trace system. An embodiment of such a method comprises generating a plurality of trigger packets from a plurality of trigger sources on a system on chip. Each trigger packet defines a corresponding event and a corresponding system-generated timestamp. The plurality of trigger packets are distributed from the corresponding trigger sources to a centralized logic analyzer via a variable latency bus interconnect. The received triggered packets are re-ordered according to the corresponding system-generated timestamps into an order in which the corresponding events occurred. The received trigger packets are replayed in the order in which the corresponding events occurred.

6. 发明申请

US20170366468A1 LOW LATENCY RE-TIMER 审中-公开
公开(公告)号：US20170366468A1
公开(公告)日：2017-12-21
申请号：US15465396
申请日：2017-03-21
申请人： Intel Corporation
发明人： Ehud SHOOR , Ari SHARON
IPC分类号： H04L12/863 , H04L1/00 , H04L7/033 , H04L25/03
CPC分类号： H04L47/6245 , G06F1/04 , G06F13/40 , H04B15/00 , H04L1/0018 , H04L25/03273 , H04L49/90
摘要： Described is a low latency re-timer for systems supporting spread spectrum clocking. The re-timer comprises: a first clock frequency estimator to estimate a frequency of a receive clock (RX CLK) and to provide a first timestamp associated with a first clock that underwent spread spectrum; a second clock frequency estimator to estimate a frequency of a transmit clock (TX CLK) and to provide a second timestamp associated with a second clock that underwent spread spectrum; and a comparator to compare the first timestamp with the second timestamp.

7. 发明授权

US09736086B1 Multi-function, multi-protocol FIFO for high-speed communication 有权
公开(公告)号：US09736086B1
公开(公告)日：2017-08-15
申请号：US13098361
申请日：2011-04-29
申请人： Huy Ngo , Keith Duwel , Vinson Chan , Divya Vijayaraghavan , Curt Wortman
发明人： Huy Ngo , Keith Duwel , Vinson Chan , Divya Vijayaraghavan , Curt Wortman
IPC分类号： H04L12/861
CPC分类号： H04L49/90 , H04L47/6245
摘要： Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

8. 发明申请

US20170180519A1 NETWORK DEVICE AND METHOD FOR OUTPUTTING DATA TO BUS WITH DATA BUS WIDTH AT EACH CYCLE BY GENERATING END OF PACKET AND START OF PACKET AT DIFFERENT CYCLES 有权
公开(公告)号：US20170180519A1
公开(公告)日：2017-06-22
申请号：US15450006
申请日：2017-03-05
申请人： MEDIATEK INC.
发明人： Chi-Feng Lin , Wei-Jen Chen
IPC分类号： H04L29/08 , H04L12/40 , H04L12/863 , H04L12/811
CPC分类号： H04L69/324 , H04L12/40 , H04L47/38 , H04L47/6245
摘要： A method used in a network device for outputting data to a bus with a data bus width at each cycle includes: using a packet generating circuit for generating idle data after an end of packet for a packet at a cycle and generating a start of packet for a next packet at a different cycle; and using an inter-packet gap (IPG) generating circuit for receiving data transmitted from the packet generating circuit, dynamically writing the received data into the buffer, and inserting a gap of idle data between the end of packet and the start of packet according to the end of packet and the idle data generated by the packet generating circuit.

9. 发明授权

US09628396B2 Network device and method for outputting data to bus with data bus width at each cycle by generating end of packet and start of packet at different cycles 有权
公开(公告)号：US09628396B2
公开(公告)日：2017-04-18
申请号：US14258021
申请日：2014-04-22
申请人： MEDIATEK INC.
发明人： Chi-Feng Lin , Wei-Jen Chen
IPC分类号： H04L12/701 , H04L12/811
CPC分类号： H04L69/324 , H04L12/40 , H04L47/38 , H04L47/6245
摘要： A method used in a network device for outputting data to a bus with a data bus width at each cycle includes: using a packet generator for generating idle data after an end of packet for a packet at a cycle and generating a start of packet for a next packet at a different cycle; and using an inter-packet gap (IPG) generator for receiving data transmitted from the packet generator, dynamically writing the received data into the buffer, and inserting a gap of idle data between the end of packet and the start of packet according to the end of packet and the idle data generated by the packet generator.

10. 发明授权

US09455938B2 Streaming methods and systems for network devices 有权
标题翻译：网络设备的流式传输方法和系统
公开(公告)号：US09455938B2
公开(公告)日：2016-09-27
申请号：US14519977
申请日：2014-10-21
申请人： KIP CR P1 LP
发明人： Keith M. Arroyo , Stephen K. Wilson
IPC分类号： H04L12/861 , H04L29/08 , G06F3/06
CPC分类号： H04L49/9005 , G06F3/0626 , G06F3/0659 , G06F3/067 , H04L45/60 , H04L47/6245 , H04L49/90 , H04L67/1097 , H04L69/18
摘要： A system and method are disclosed for processing commands to network target devices through a SCSI router in a Fiber Channel network having a plurality of Fiber Channel hosts. The system may be configured to receive a command, and determine that the command requires a transfer of data larger than a threshold size. The system may also be configured to receive a plurality of data blocks associated with the command, store the plurality of data blocks in at least one buffer, and determine if there is an initial amount of data in the at least one buffer. The system may be further configured to forward at least one of the plurality data blocks, and request an additional data block associated with the command.
摘要翻译：公开了一种用于处理通过具有多个光纤通道主机的光纤通道网络中的SCSI路由器来对目标设备进行网络的命令的系统和方法。该系统可以被配置为接收命令，并且确定该命令需要大于阈值大小的数据传送。系统还可以被配置为接收与命令相关联的多个数据块，将多个数据块存储在至少一个缓冲器中，并且确定在至少一个缓冲器中是否存在初始数据量。该系统还可以被配置为转发多个数据块中的至少一个，并且请求与该命令相关联的附加数据块。

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