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    • 9. 发明授权
    • Accelerator circuit and image processing apparatus
    • 加速器电路和图像处理装置
    • US09363412B2
    • 2016-06-07
    • US14681290
    • 2015-04-08
    • Hideki SugimotoAkihiro MatsuokaShimpei Sonoda
    • Hideki SugimotoAkihiro MatsuokaShimpei Sonoda
    • G06F15/00G06F1/00G06K1/00G06K15/00H04N1/32G06T1/20
    • H04N1/32561G06T1/20
    • An accelerator circuit for an image processing apparatus includes a buffer circuit that temporarily stores image data obtained from N (N>1) data sources and an arithmetic circuit that performs a predetermined arithmetic operation on pixel data. The buffer circuit includes N buffer memories and N 2D registers associated with the respective N data sources, a control circuit, and a selector. Each buffer memory temporarily stores image data obtained from a corresponding one of the N data sources. Each 2D register temporarily stores pixel data, which is a part of image data stored in a corresponding one of the N buffer memories, of an area of a predetermined size. The selector is controlled by the control circuit so as to select, when pixel data is stored in one of the N 2D registers, the pixel data and send the pixel data to the arithmetic circuit.
    • 一种用于图像处理装置的加速器电路包括缓冲电路,其临时存储从N(N> 1)个数据源获得的图像数据和对像素数据执行预定算术运算的运算电路。 缓冲电路包括与各个N个数据源相关联的N个缓冲存储器和N个2D寄存器,一个控制电路和一个选择器。 每个缓冲存储器临时存储从N个数据源中的相应一个获得的图像数据。 每个2D寄存器临时存储作为预定大小的区域中存储在相应的一个N个缓冲存储器中的图像数据的一部分的像素数据。 选择器由控制电路控制,以便当像素数据存储在N 2D寄存器之一中时,选择像素数据并将像素数据发送到运算电路。
    • 10. 发明申请
    • IMAGE PROCESSING APPARATUS, METHOD FOR PERFORMING SPECIFIC PROCESS, AND COMPUTER-READABLE STORAGE MEDIUM FOR COMPUTER PROGRAM
    • 图像处理装置,用于执行特定过程的方法和用于计算机程序的计算机可读存储介质
    • US20160127604A1
    • 2016-05-05
    • US14928006
    • 2015-10-30
    • Konica Minolta, Inc.
    • Tatsuya Kawano
    • H04N1/32G06K15/02H04N1/04
    • H04N1/32475G06F9/5044G06K15/1848H04N1/04H04N1/32561H04N2201/0094
    • An image processing apparatus includes a processor having a plurality of cores, each having different specifications. The image processing apparatus further includes a first estimator that estimates a processing capability of each of the plurality of cores, a second estimator that estimates, based on the processing capability of each of the plurality of cores, a required time for each of the plurality of cores to perform a specific process, and a controller. The plurality of cores comprises one or more candidate cores. The required time for each of the one or more candidate cores is equal to or less than a threshold. The controller controls one of the one or more candidate cores to perform the specific process. The required time of the candidate core that performs the specific process is the longest among the one or more candidate cores.
    • 图像处理装置包括具有多个芯的处理器,每个芯具有不同的规格。 所述图像处理装置还包括估计所述多个核心中的每一个的处理能力的第一估计器,第二估计器,其基于所述多个核心中的每一个的处理能力来估计所述多个核心中的每一个的所需时间 执行特定进程的核心和控制器。 多个核心包括一个或多个候选核心。 一个或多个候选核心中的每一个的所需时间等于或小于阈值。 控制器控制一个或多个候选核心中的一个来执行特定过程。 执行特定处理的候选核心所需的时间在一个或多个候选核心中是最长的。