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1. 发明申请

US20170294414A1 COMPUTER MODULES WITH SMALL THICKNESSES AND ASSOCIATED METHODS OF MANUFACTURING 审中-公开
公开(公告)号：US20170294414A1
公开(公告)日：2017-10-12
申请号：US15626843
申请日：2017-06-19
申请人： Micron Technology, Inc.
发明人： Kevin Gibbons , Tracy V. Reynolds , David J. Corisis
IPC分类号： H01L25/065 , H05K1/18 , H05K3/34 , H01L25/10
CPC分类号： H01L25/0657 , H01L24/73 , H01L24/83 , H01L25/105 , H01L25/18 , H01L2224/16145 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06555 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2225/1088 , H01L2924/00011 , H01L2924/00014 , H01L2924/14 , H01L2924/19104 , H05K1/111 , H05K1/182 , H05K1/183 , H05K3/3436 , H05K7/02 , H05K2201/10515 , H05K2201/10545 , H05K2201/10727 , H05K2203/1572 , Y10T29/49126 , Y10T29/4913 , H01L2224/32145 , H01L2224/48227 , H01L2924/00012 , H01L2224/32225 , H01L2924/00 , H01L2224/0401
摘要： Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. The computer modules can also include a microelectronic package carried by the module substrate. The microelectronic package includes a semiconductor die carried by a package substrate. At least a portion of the semiconductor die extends into the substrate material via the aperture.

2. 发明授权

US09635794B2 Method and apparatus for attachment of integrated circuits 有权
公开(公告)号：US09635794B2
公开(公告)日：2017-04-25
申请号：US13716890
申请日：2012-12-17
申请人： TRW Automotive US LLC
发明人： Mike Babala , Jesse Theissen
IPC分类号： H05K13/08 , H05K3/32 , H05K13/04 , H01L21/66 , H05K1/02 , H05K1/18
CPC分类号： H05K13/0465 , H01L22/14 , H01L22/34 , H01L2924/0002 , H05K1/0268 , H05K1/181 , H05K2201/10151 , H05K2201/10727 , H01L2924/00
摘要： Method and apparatus for bonding an electrical circuit component onto a substrate. A first electrically conductive bonding pad is formed on the component, and a second electrically conductive bonding pad is formed on the substrate. One of said first and second bonding pads is physically split into at least two parts, with electrical discontinuity between the two parts. An electrically conductive bond is formed between the first and second bonding pads such that electrical continuity is established from one part of the one bonding pad, through the other of the bonding pads, and through the second part of the one bonding pad. The integrity of the electrically conductive bond is evaluated by testing electrical continuity between the at least two parts.

3. 发明授权

US09554453B2 Printed circuit board structure with heat dissipation function 有权
标题翻译：印刷电路板结构具有散热功能
公开(公告)号：US09554453B2
公开(公告)日：2017-01-24
申请号：US13777369
申请日：2013-02-26
申请人： MediaTek Inc.
发明人： Shu-Wei Hsiao
IPC分类号： H05K1/00 , H05K1/02
CPC分类号： H05K1/0209 , H05K1/0206 , H05K2201/09609 , H05K2201/09781 , H05K2201/0979 , H05K2201/10727 , H05K2201/10969
摘要： A printed circuit board (PCB) structure with a heat dissipation function is provided, including: a package substrate; a landing pad formed over a portion of the package substrate from a first surface thereof, wherein the landing pad has a rectangular configuration and has a plurality of corners; a plurality of ground traces formed over various portions of the package substrate, physically connecting to the bond pad from at least two of the corners thereof, respectively; a first through hole formed through the landing pad and the package substrate from substantially a center portion of the bonding pad; and a plurality of second through holes formed through the landing pad and the package substrate from substantially one of the corners of the bonding pad, wherein the second through holes are adjacent to the ground traces, respectively.
摘要翻译：提供具有散热功能的印刷电路板（PCB）结构，包括：封装基板; 从所述封装基板的第一表面形成在所述封装基板的一部分上的着陆焊盘，其中所述着陆焊盘具有矩形构造并且具有多个拐角; 形成在所述封装衬底的各个部分上的多个接地迹线，分别从其至少两个角部物理连接到所述接合焊盘; 从接合焊盘的大致中心部分穿过着陆焊盘和封装衬底形成的第一通孔; 以及多个第二通孔，其通过所述着陆焊盘和所述封装基板从所述接合焊盘的大致角部形成，其中所述第二通孔分别与所述接地迹线相邻。

4. 发明申请

US20170019998A1 CIRCUIT BOARD ASSEMBLY AND METHOD OF MANUFACTURING SAME 有权
标题翻译：电路板组件及其制造方法
公开(公告)号：US20170019998A1
公开(公告)日：2017-01-19
申请号：US14801422
申请日：2015-07-16
申请人： Delphi Technologies, Inc.
发明人： Rodrigo Franco
IPC分类号： H05K1/14 , H05K1/11 , H05K3/40 , H05K3/36 , H05K3/42 , H05K1/18 , H05K3/32
CPC分类号： H05K1/144 , H05K1/111 , H05K1/115 , H05K1/14 , H05K1/141 , H05K1/145 , H05K1/181 , H05K1/183 , H05K3/32 , H05K3/3442 , H05K3/36 , H05K3/4007 , H05K3/429 , H05K2201/045 , H05K2201/09036 , H05K2201/09181 , H05K2201/095 , H05K2201/10166 , H05K2201/10727
摘要： The circuit board assembly includes a first circuit board having a first plurality of electronic components attached to a major surface of the first circuit board. The first plurality of electronic components is electrically interconnected to a first plurality of conductive pads defined on the major surface of the first circuit board. A second circuit board has a second plurality of electronic components attached to a first major surface of the second circuit board. The second plurality of electronic components is electrically interconnected to a second plurality of conductive pads defined on a second major surface of the second circuit board. The first and second circuit board are attached by coupling the first and second plurality of conductive pads. A portion of the first plurality of electronic components on the first circuit board are disposed within a cavity defined by the second major surface of the second circuit board.
摘要翻译：电路板组件包括具有附接到第一电路板的主表面的第一多个电子部件的第一电路板。第一组多个电子部件电连接到限定在第一电路板的主表面上的第一多个导电焊盘。第二电路板具有附接到第二电路板的第一主表面的第二多个电子部件。所述第二多个电子部件电连接到限定在所述第二电路板的第二主表面上的第二多个导电焊盘。第一和第二电路板通过联接第一和第二多个导电焊盘而附接。第一电路板上的第一多个电子部件的一部分设置在由第二电路板的第二主表面限定的空腔内。

5. 发明申请

US20160338200A1 SOLDER VOID REDUCTION BETWEEN ELECTRONIC PACKAGES AND PRINTED CIRCUIT BOARDS 有权
标题翻译：电子封装和印刷电路板之间的焊接失电
公开(公告)号：US20160338200A1
公开(公告)日：2016-11-17
申请号：US15220771
申请日：2016-07-27
申请人： International Business Machines Corporation
发明人： Phillip D. Isaacs
IPC分类号： H05K1/18 , H05K1/11 , H05K3/42 , H05K1/02 , H05K3/34
CPC分类号： H05K1/181 , H05K1/0206 , H05K1/0207 , H05K1/0209 , H05K1/0215 , H05K1/114 , H05K1/116 , H05K3/3431 , H05K3/3436 , H05K3/429 , H05K2201/09572 , H05K2201/10727 , H05K2201/10969 , H05K2203/0207 , H05K2203/176 , Y10T29/49144
摘要： An apparatus includes a printed circuit board. The printed circuit board includes at least one conductive layer on top a first dielectric layer, wherein the at least one conductive layer comprises at least one of a ground plane and a power plane. The printed circuit board includes a second dielectric layer on top of the at least one conductive layer. The printed circuit board includes a thermal pad on top of the second dielectric layer. The printed circuit board is fabricated by forming at least one plated through hole for electrically coupling the thermal pad to the at least one conductive layer. The printed circuit board is fabricated by backdrilling the at least one plated through hole to remove a portion of the conductive material, wherein subsequent to the backdrilling the conductive material remaining in the at least one plated through hole electrically couples one or more of the at least one conductive layer to the thermal pad.
摘要翻译：一种装置包括印刷电路板。印刷电路板包括在第一电介质层的顶部上的至少一个导电层，其中至少一个导电层包括接地平面和电源平面中的至少一个。印刷电路板包括在至少一个导电层的顶部上的第二电介质层。印刷电路板包括位于第二电介质层顶部的散热焊盘。通过形成至少一个电镀通孔来制造印刷电路板，用于将热垫电耦合到至少一个导电层。印刷电路板通过对至少一个电镀通孔进行回钻以除去导电材料的一部分来制造，其中在后钻之后，保留在至少一个电镀通孔中的导电材料电耦合至少一个或多个一个导电层到散热垫。

6. 发明申请

US20160295698A1 SEMICONDUCTOR PACKAGE MODULES, MEMORY CARDS INCLUDING THE SAME, AND ELECTRONIC SYSTEMS INCLUDING THE SAME 有权
标题翻译：半导体封装模块，包括其的存储卡，以及包括其的电子系统
公开(公告)号：US20160295698A1
公开(公告)日：2016-10-06
申请号：US14813359
申请日：2015-07-30
申请人： SK hynix Inc.
发明人： Jung Tae JEONG
IPC分类号： H05K1/18 , H05K1/09 , H05K1/14 , H05K1/11
CPC分类号： H05K1/181 , H01L23/49811 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/73 , H01L2224/13101 , H01L2224/16225 , H01L2224/32225 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/73204 , H01L2924/15174 , H01L2924/181 , H01L2924/19107 , H05K3/3436 , H05K2201/10287 , H05K2201/10719 , H05K2201/10727 , H05K2203/049 , Y02P70/613 , H01L2924/00012 , H01L2924/014 , H01L2924/00014
摘要： A semiconductor package module may include a first substrate, and a second substrate disposed to face the first substrate. The semiconductor package module may include an interconnection member electrically connecting the first substrate to the second substrate and including a plurality of wires. Portions of the plurality of wires may be twisted and wound together and may be bent to extend in a predetermined direction.
摘要翻译：半导体封装模块可以包括第一衬底和布置成面对第一衬底的第二衬底。半导体封装模块可以包括将第一衬底电连接到第二衬底并且包括多个电线的互连构件。多个线的一部分可以被扭绞并缠绕在一起，并且可以被弯曲以沿预定方向延伸。

7. 发明申请

US20160141279A1 METHODS FOR PERFORMING EXTENDED WAFER-LEVEL PACKAGING (eWLP) AND eWLP DEVICES MADE BY THE METHODS 审中-公开
标题翻译：用于执行扩展水平包装（eWLP）和方法制造的eWLP器件的方法
公开(公告)号：US20160141279A1
公开(公告)日：2016-05-19
申请号：US15002333
申请日：2016-01-20
申请人： Avago Technologies General IP (Singapore) Pte. Ltd.
发明人： Detlef Bernd Krabe , Josef Wittl
IPC分类号： H01L25/16 , H01S5/022 , H01L31/02 , H01L23/538 , H01L23/31 , H01L31/167
CPC分类号： H01L25/167 , H01L21/568 , H01L23/3114 , H01L23/5386 , H01L24/19 , H01L24/20 , H01L24/25 , H01L24/96 , H01L24/97 , H01L25/165 , H01L31/02002 , H01L31/0203 , H01L31/16 , H01L31/167 , H01L31/18 , H01L33/005 , H01L33/52 , H01L2224/04105 , H01L2224/06181 , H01L2224/11 , H01L2224/12105 , H01L2224/18 , H01L2224/24137 , H01L2224/2518 , H01L2224/9222 , H01L2933/0033 , H01L2933/005 , H01S5/0201 , H01S5/02248 , H01S5/02272 , H05K1/181 , H05K2201/10121 , H05K2201/10727 , H05K2201/10977 , Y02P70/521
摘要： Embedded Wafer-Level Packaging (eWLP) devices, packages and assemblies and methods of making them are provided. The eWLP methods allow back side electrical and/or thermal connections to be easily and economically made at the eWLP wafer level without having to use thru-mold vias (TMVs) or thru-silicon vias (TSVs) to make such connections. In order to create TMVs, processes such as reactive ion etching or laser drilling followed metallization are needed, which present difficulties and increase costs. In addition, the eWLP methods allow electrical and optical interfaces to be easily and economically formed on the front side and/or on the back side of the eWLP wafer, which allows the eWLP methods to be used to form optoelectronic devices having a variety of useful configurations.
摘要翻译：提供嵌入式晶圆级封装（eWLP）器件，封装和组件及其制造方法。 eWLP方法允许在eWLP晶片级别容易且经济地进行背面电气和/或热连接，而不必使用通孔（TMV）或通硅硅通孔（TSV）来进行这种连接。为了创建TMV，需要诸如反应离子蚀刻或激光钻孔等过程进行金属化处理，从而存在困难并增加成本。此外，eWLP方法允许在eWLP晶片的前侧和/或背面容易且经济地形成电和光学界面，这允许eWLP方法形成具有各种有用的光电器件配置

8. 发明申请

US20150262983A1 METHODS FOR PERFORMING EXTENDED WAFER-LEVEL PACKAGING (eWLP) AND eWLP DEVICES MADE BY THE METHODS 有权
标题翻译：用于执行扩展水平包装（eWLP）和方法制造的eWLP器件的方法
公开(公告)号：US20150262983A1
公开(公告)日：2015-09-17
申请号：US14213342
申请日：2014-03-14
申请人： Avago Technologies General IP (Singapore) Pte. Ltd.
发明人： Detlef Bernd Krabe , Josef Wittl
IPC分类号： H01L25/16 , H01L31/18 , H01L31/16 , H05K1/18 , H01L33/52 , H01S5/022 , H01S5/02 , H01L33/00 , H01L31/0203
CPC分类号： H01L25/167 , H01L21/568 , H01L23/3114 , H01L23/5386 , H01L24/19 , H01L24/20 , H01L24/25 , H01L24/96 , H01L24/97 , H01L25/165 , H01L31/02002 , H01L31/0203 , H01L31/16 , H01L31/167 , H01L31/18 , H01L33/005 , H01L33/52 , H01L2224/04105 , H01L2224/06181 , H01L2224/11 , H01L2224/12105 , H01L2224/18 , H01L2224/24137 , H01L2224/2518 , H01L2224/9222 , H01L2933/0033 , H01L2933/005 , H01S5/0201 , H01S5/02248 , H01S5/02272 , H05K1/181 , H05K2201/10121 , H05K2201/10727 , H05K2201/10977 , Y02P70/521
摘要： Methods are provided for making embedded Wafer-Level Packaging (eWLP) devices, packages and assemblies. The eWLP methods allow back side electrical and/or thermal connections to be easily and economically made at the eWLP wafer level without having to use thru-mold vias (TMVs) or thru-silicon vias (TSVs) to make such connections. In order to create TMVs, processes such as reactive ion etching or laser drilling followed metallization are needed, which present difficulties and increase costs. In addition, the eWLP methods allow electrical and optical interfaces to be easily and economically formed on the front side and/or on the back side of the eWLP wafer, which allows the eWLP methods to be used to form optoelectronic devices having a variety of useful configurations.
摘要翻译：提供了嵌入式晶圆级封装（eWLP）器件，封装和组件的方法。 eWLP方法允许在eWLP晶片级别容易且经济地进行背面电气和/或热连接，而不必使用通孔（TMV）或通硅硅通孔（TSV）来进行这种连接。为了创建TMV，需要诸如反应离子蚀刻或激光钻孔等过程进行金属化处理，从而存在困难并增加成本。此外，eWLP方法允许在eWLP晶片的前侧和/或背面容易且经济地形成电和光学界面，这允许eWLP方法形成具有各种有用的光电器件配置

9. 发明申请

US20150255383A1 MOUNTING MEMBER, ELECTRONIC COMPONENT, AND METHOD FOR MANUFACTURING MODULE 有权
标题翻译：安装构件，电子元件和制造模块的方法
公开(公告)号：US20150255383A1
公开(公告)日：2015-09-10
申请号：US14636850
申请日：2015-03-03
申请人： CANON KABUSHIKI KAISHA
发明人： Ichiro Kataoka , Osamu Hamamoto , Kazuya Notsu , Koji Tamura , Kunihiko Minegishi
IPC分类号： H01L23/498 , H01L23/00
CPC分类号： H01L23/49838 , H01L23/49811 , H01L23/49866 , H01L24/48 , H01L24/85 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/15153 , H01L2924/15173 , H01L2924/15174 , H01L2924/15184 , H01L2924/15313 , H01L2924/16195 , H01L2924/181 , H05K1/0204 , H05K1/111 , H05K3/3436 , H05K2201/094 , H05K2201/09781 , H05K2201/10719 , H05K2201/10727 , H05K2203/0465 , H01L2224/45099 , H01L2924/00012
摘要： A mounting member includes a plurality of internal connecting portions, each of which is electrically connected to an electronic device, and a plurality of external connecting portions, each of which is soldered, wherein the plurality of external connecting portions include a first connecting portion in communication with at least any of the plurality of internal connecting portions, and a second connecting portion different from the first connecting portion, and surfaces of the first connecting portion and the second connecting portion include gold layers, and a thickness of the gold layer of the second connecting portion is smaller than a thickness of the gold layer of the first connecting portion.
摘要翻译：安装构件包括多个内部连接部分，每个内部连接部分电连接到电子设备，以及多个外部连接部分，每个外部连接部分被焊接，其中多个外部连接部分包括连通的第一连接部分与多个内部连接部分中的至少任一个以及与第一连接部分不同的第二连接部分，并且第一连接部分和第二连接部分的表面包括金层，并且第二连接部分的金层的厚度连接部分小于第一连接部分的金层的厚度。

10. 发明申请

US20150069113A1 VCSEL Packaging 有权
标题翻译： VCSEL包装
公开(公告)号：US20150069113A1
公开(公告)日：2015-03-12
申请号：US14479325
申请日：2014-09-07
申请人： PRINCETON OPTRONICS INC.
发明人： Qing Wang , Jean-Francois Seurin , Chuni Lal Ghosh , Laurence Watkins
IPC分类号： H01S5/022 , B23K1/00 , H01S5/00
CPC分类号： H01S5/02272 , B23K1/0016 , B23K1/012 , B23K2101/42 , H01L2224/16225 , H01L2224/48091 , H01L2224/49175 , H01S5/0042 , H01S5/02276 , H01S5/423 , H05K1/0206 , H05K3/3436 , H05K3/3494 , H05K2201/10121 , H05K2201/10727 , H05K2203/085 , Y02P70/613 , H01L2924/00014
摘要： A process to bond VCSEL arrays to submounts and printed circuit boards is provided. The process is particularly suited to large area thin and ultra-thin VCSEL arrays susceptible to bending and warping. The process integrates a flatness measurement step and applying appropriate combination of pressure prior to bonding the VCSEL array to the submount or a printed circuit using a vacuum flux-less bonding process. The process is very promising in making very good quality bonding between the VCSEL array and a submount or a printed circuit board. The process is applied to construct optical modules with improved flatness that may be integrated with other electronic components in constructing optoelectronic systems.
摘要翻译：提供了将VCSEL阵列绑定到底座和印刷电路板的过程。该工艺特别适用于容易弯曲和翘曲的大面积薄型和超薄型VCSEL阵列。该过程集成了平坦度测量步骤，并且在使用真空无焊接接合工艺将VCSEL阵列与基座或印刷电路结合之前应用适当的压力组合。该过程非常有希望在VCSEL阵列与底座或印刷电路板之间进行非常好的质量接合。该方法应用于构建具有改进的平坦度的光学模块，其可以与构建光电子系统的其它电子部件集成。

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