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1. 发明申请

US20180175579A1 METHOD AND SYSTEM FOR MUTLILINE MIR-IR LASER 审中-公开
公开(公告)号：US20180175579A1
公开(公告)日：2018-06-21
申请号：US15884271
申请日：2018-01-30
申请人： THE UAB RESEARCH FOUNDATION
发明人： Sergey B. Mirov , Vladimir V. Fedorov
IPC分类号： H01S3/08 , H01S3/0941 , C30B31/02 , H01S3/06 , H01S3/16 , H01S3/117 , H01S3/115 , H01S3/108 , H01S3/1055 , C30B31/00 , H01S3/094 , H01S3/00 , H01S3/113
CPC分类号： H01S3/0805 , C30B29/48 , C30B31/00 , C30B31/02 , H01S3/0014 , H01S3/0604 , H01S3/0617 , H01S3/0627 , H01S3/08009 , H01S3/08086 , H01S3/094038 , H01S3/094042 , H01S3/094046 , H01S3/09415 , H01S3/1055 , H01S3/108 , H01S3/113 , H01S3/115 , H01S3/117 , H01S3/162 , H01S3/1623 , H01S3/1628 , H01S2301/04 , Y10S438/917
摘要： A method of performing spatial separation of different wavelengths in a single laser cavity includes generating, from a pump radiation source, pump radiations in spatially separate channels and focusing the generated pump radiations in the spatially separate channels towards an active gain medium having amplification spectra. The method also includes emitting from the active gain medium, amplified radiations of the spatially separate channels, each channel of the spatially separate channels representing a corresponding wavelength and focusing the emitted amplified radiations of the spatially separated channels towards an aperture. The method further includes suppressing, at the aperture, an off-axis mode of the amplified radiations of the spatially separate channels, diffracting the amplified radiations of the spatially separate channels received through the aperture to provide diffracted radiations and returning a portion of the diffracted radiations back to the aperture, and collimating the diffracted radiations of the spatially separate channel.

2. 发明授权

US08193537B2 Optically controlled silicon carbide and related wide-bandgap transistors and thyristors 有权
标题翻译：光控碳化硅和相关宽带隙晶体管和晶闸管
公开(公告)号：US08193537B2
公开(公告)日：2012-06-05
申请号：US11764606
申请日：2007-06-18
申请人： Michael S. Mazzola
发明人： Michael S. Mazzola
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L31/028 , H01L31/0312 , H01L31/09 , H01L31/1105 , H03K17/78 , Y10S438/917 , Y10S438/931
摘要： An optically active material is used to create power devices and circuits having significant performance advantages over conventional methods for affecting optical control of power electronics devices and circuits. A silicon-carbide optically active material is formed by compensating shallow donors with the boron related D-center. The resulting material can be n-type or p-type but it is distinguished from other materials by the ability to induce persistent photoconductivity in it when illuminated by electromagnetic radiation with a photon energy in excess of the threshold energy required to photoexcite electrons from the D-center to allowed states close to the conduction band edge, which varies from polytype to polytype.
摘要翻译：与用于影响电力电子设备和电路的光学控制的常规方法相比，使用光学活性材料来产生具有显着性能优点的功率器件和电路。通过用硼相关的D中心补偿浅供体来形成碳化硅光学活性材料。所得到的材料可以是n型或p型，但是当通过电磁辐射照射时能够引起持续光电导的能力与其它材料不同，其中光子能量超过光电从D激发电子所需的阈值能量 - 允许状态接近导带边缘，其从多形型到多型变化。

3. 发明申请

US20100022049A1 Mid-IR Microchip Laser: ZnS:Cr2+ Laser with Saturable Absorber Material 审中-公开
标题翻译：中红外激光器：具有可饱和吸收材料的ZnS：Cr2 +激光器
公开(公告)号：US20100022049A1
公开(公告)日：2010-01-28
申请号：US12485826
申请日：2009-06-16
申请人： Sergey B. Mirov , Vladimir V. Fedorov
发明人： Sergey B. Mirov , Vladimir V. Fedorov
IPC分类号： H01L21/06 , H01L21/71 , H01L21/22 , H01L21/00
CPC分类号： H01S3/0805 , C30B29/48 , C30B31/00 , C30B31/02 , H01S3/0014 , H01S3/0604 , H01S3/0617 , H01S3/0627 , H01S3/08009 , H01S3/08086 , H01S3/094038 , H01S3/094042 , H01S3/094046 , H01S3/09415 , H01S3/1055 , H01S3/108 , H01S3/113 , H01S3/115 , H01S3/117 , H01S3/162 , H01S3/1623 , H01S3/1628 , H01S2301/04 , Y10S438/917
摘要： A method of fabrication of laser gain material and utilization of such media includes the steps of introducing a transitional metal, preferably Cr2+ thin film of controllable thickness on the ZnS crystal facets after crystal growth by means of pulse laser deposition or plasma sputtering, thermal annealing of the crystals for effective thermal diffusion of the dopant into the crystal volume with a temperature and exposition time providing the highest concentration of the dopant in the volume without degrading laser performance due to scattering and concentration quenching, and formation of a microchip laser either by means of direct deposition of mirrors on flat and parallel polished facets of a thin Cr:ZnS wafer or by relying on the internal reflectance of such facets. The gain material is susceptible to utilization of direct diode or fiber laser pumping of a microchip laser with a level of power density providing formation of positive lens and corresponding cavity stabilization as well as threshold population inversion in the laser material. Multiple applications of the laser material are contemplated in the invention.
摘要翻译：激光增益材料的制造方法和这种介质的利用方法包括以下步骤：通过脉冲激光沉积或等离子溅射在晶体生长之后，在ZnS晶面上引入可控厚度的过渡金属，优选Cr 2+薄膜，热退火用于在温度和曝光时间内有效地将掺杂剂热扩散到晶体体积中的晶体在体积中提供掺杂剂的最高浓度而不降低由于散射和浓缩猝灭引起的激光性能，以及通过以下方式形成微芯片激光器：将反射镜直接沉积在薄的Cr：ZnS晶片的平坦和平行的抛光面上，或依赖于这些面的内部反射。增益材料易于利用具有功率密度水平的微芯片激光器的直接二极管或光纤激光泵浦，其提供形成正透镜并且相应的腔稳定以及激光材料中的阈值群体反转。在本发明中考虑了激光材料的多种应用。

4. 发明申请

US20060128082A1 Gate control and endcap improvement 有权
标题翻译：门控和端帽改进
公开(公告)号：US20060128082A1
公开(公告)日：2006-06-15
申请号：US11012414
申请日：2004-12-15
申请人： Harry Chuang , Kong-Beng Thei
发明人： Harry Chuang , Kong-Beng Thei
IPC分类号： H01L21/338
CPC分类号： H01L21/28123 , H01L21/823437 , H01L27/0207 , H01L29/4966 , Y10S438/917
摘要： A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric layer are etched thereby forming gate structures and dummy patterns, wherein at least one of the dummy patterns has at least a portion in the active region. The first photo resist is removed. A second photo resist is formed covering the gate structures. The dummy patterns unprotected by the second photo resist are removed. The second photo resist is then removed.
摘要翻译：形成半导体结构的方法包括以下步骤。在有源区中的衬底上形成栅介电层。栅极电极层形成在栅极介电层上。在栅电极层上形成第一光刻胶。蚀刻栅极电极层和电介质层，从而形成栅极结构和虚拟图案，其中虚拟图案中的至少一个具有活性区域中的至少一部分。第一个光刻胶被去除。形成覆盖栅极结构的第二光致抗蚀剂。去除不受第二光致抗蚀剂保护的虚拟图案。然后移除第二个光刻胶。

5. 发明申请

US20050042386A1 Method of production of nano particle dispersed composite material 有权
标题翻译：纳米颗粒分散复合材料的生产方法
公开(公告)号：US20050042386A1
公开(公告)日：2005-02-24
申请号：US10864881
申请日：2004-06-10
申请人： Masahiro Nunoshita , Ichiro Yamashita , Shigeo Yoshii
发明人： Masahiro Nunoshita , Ichiro Yamashita , Shigeo Yoshii
IPC分类号： B05D3/02 , H01L21/266 , H01L29/12 , H01L29/15
CPC分类号： H01L29/127 , B82Y10/00 , B82Y30/00 , C01P2004/64 , H01L21/266 , H01L29/158 , Y10S438/917 , Y10S438/918 , Y10S438/962
摘要： A method of the production of a nanoparticle dispersed composite material capable of controlling a particle size and a three dimensional arrangement of the nanoparticles is provided. The method of the production of a nanoparticle dispersed composite material of the present invention includes a step (a) of arranging a plurality of core fine particle-protein complexes having a core fine particle, which comprises an inorganic material, internally included within a protein on the top surface of a substrate, a step (b) of removing the protein, a step (c) of conducting ion implantation from the top surface of the substrate, and a step (d) of forming nanoparticles including the ion implanted by the ion implantation as a raw material, inside of the substrate.
摘要翻译：提供了能够控制纳米颗粒的粒度和三维排列的纳米颗粒分散复合材料的制造方法。制备本发明的纳米颗粒分散复合材料的方法包括：将包含内部包含在蛋白质内的无机材料的多个具有核心细颗粒的核心细颗粒 - 蛋白复合物排列在衬底的顶表面，去除蛋白质的步骤（b），从衬底的顶表面进行离子注入的步骤（c）和形成纳米颗粒的步骤（d），其包括由离子注入的离子作为原料植入，在基板的内部。

6. 发明授权

US5960322A Suppression of boron segregation for shallow source and drain junctions in semiconductors 失效
标题翻译：抑制半导体中浅源极和漏极结的硼偏析
公开(公告)号：US5960322A
公开(公告)日：1999-09-28
申请号：US994308
申请日：1997-12-19
申请人： Qi Xiang , Geoffrey Yeap , Srinath Krishnan , Ming-Ren Lin
发明人： Qi Xiang , Geoffrey Yeap , Srinath Krishnan , Ming-Ren Lin
IPC分类号： H01L21/265 , H01L21/336 , H01L21/31 , H01L21/469
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/6656 , Y10S438/917
摘要： A method in the manufacture of ultra-large scale integrated circuit semiconductor devices suppresses boron loss due to segregation into the screen oxide during the boron activation rapid thermal anneal. A nitridation of the screen oxide is used to incorporate nitrogen into the screen oxide layer prior to boron implantation for ultra-shallow, source and drain extension junctions. A second nitridation of a second screen oxide is used prior to boron implantation for deeper, source and drain junctions. This method significantly suppresses boron diffusion and segregation away from the silicon substrate which reduces series resistance of the complete source and drain junctions.
摘要翻译：制造超大规模集成电路半导体器件的方法抑制了硼激活快速热退火期间由于偏析到屏幕氧化物中的硼损失。在用于超浅，源极和漏极延伸结的硼注入之前，使用屏幕氧化物的氮化将氮掺入屏幕氧化物层中。在硼注入之前，使用第二屏蔽氧化物的第二次氮化用于更深，源极和漏极结。该方法显着抑制了硼扩散和离开硅衬底的偏析，从而降低了整个源极和漏极结的串联电阻。

7. 发明授权

US5595924A Technique of forming over an irregular surface a polysilicon layer with a smooth surface 失效
标题翻译：在不规则表面上形成具有光滑表面的多晶硅层的技术
公开(公告)号：US5595924A
公开(公告)日：1997-01-21
申请号：US358801
申请日：1994-12-19
申请人： Jack H. Yuan , Gheorghe Samachisa
发明人： Jack H. Yuan , Gheorghe Samachisa
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L27/11534 , H01L27/11543 , Y10S438/917 , Y10S438/947
摘要： Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.
摘要翻译：形成具有单个电池尺寸的快闪EEPROM单元阵列的技术被减少，从而增加可能形成在给定尺寸的半导体衬底上的电池数量。在该过程的几个步骤中使用电介质间隔物控制正被蚀刻或注入离子的区域，使之比通过最高分辨率光刻可以获得的更小。包括分离通道和非分离通道（无选择晶体管）类型的存储单元。示例单元采用具有分离的浮置，控制和擦除栅极的三个多晶硅层。形成具有较高导电性均匀性的存储单元栅极的技术包括沉积未掺杂的多晶硅，然后使用离子注入来引入掺杂剂。通过CVD沉积和干蚀刻在该工艺的早期阶段形成场氧化物。存储单元阵列和相邻的外围组件以协调的方式形成在单个集成电路芯片上。

8. 发明授权

US5384477A CMOS latchup suppression by localized minority carrier lifetime reduction 失效
标题翻译：通过局部少数载流子寿命降低的CMOS闭锁抑制
公开(公告)号：US5384477A
公开(公告)日：1995-01-24
申请号：US28456
申请日：1993-03-09
申请人： Constantin Bulucea , Esin Dermirlioglu , Sheldon Aronowitz
发明人： Constantin Bulucea , Esin Dermirlioglu , Sheldon Aronowitz
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L27/0921 , Y10S148/023 , Y10S438/904 , Y10S438/917
摘要： A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior Which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.
摘要翻译：描述了抑制CMOS结构中的闭锁的独特方法。可以植入在硅中显示中等水平并满足局部作用和电相容性标准的原子物质，以抑制引起闭锁的寄生双极性行为。通过CMOS结构在有源MOS器件区域之外的临界寄生双极区域可以实现少数载流子寿命的降低。实现这一目标的一个方法是在源极/漏极掺杂剂被植入之前，使用源极/漏极掩模来局部注入少数载流子寿命衰减器（MCLR）。这允许MCLR在n沟道晶体管和p沟道晶体管的不同深度或者甚至不同的物种中被引入。实现这一目标的另一种方法是要求在隔离氧化，栅极氧化或活性阈值植入完成之前，在该过程中非常早地完成覆盖MCLR植入物。

9. 发明授权

US5252512A TEOV doping of gallium arsenide 失效
标题翻译： TEOV掺杂砷化镓
公开(公告)号：US5252512A
公开(公告)日：1993-10-12
申请号：US963234
申请日：1992-10-19
申请人： Alexander J. Shuskus , Melvyn E. Cowher
发明人： Alexander J. Shuskus , Melvyn E. Cowher
IPC分类号： H01L21/205
CPC分类号： H01L21/02395 , H01L21/02546 , H01L21/02581 , H01L21/0262 , Y10S148/023 , Y10S148/04 , Y10S148/041 , Y10S148/13 , Y10S438/917 , Y10S438/918
摘要： GaAs films compensated with TEOV to reduce free electron concentration are grown having superior morphology by heating the TEOV above the temperature used in the prior art, filtering the other constituents but not the TEOV, and reducing the arsenic ambient during the preliminary heating phase.
摘要翻译：通过将TEOV加热到高于现有技术使用的温度，过滤其它成分而不是TEOV，并且在预加热阶段中降低砷的环境，生长具有TEOV补偿以减少游离电子浓度的GaAs膜以降低自由电子浓度。

10. 发明授权

US5190885A IGBT process to produce platinum lifetime control 失效
公开(公告)号：US5190885A
公开(公告)日：1993-03-02
申请号：US852932
申请日：1992-03-13
申请人： Douglas A. Pike, Jr. , Dah W. Tsang , James M. Katana
发明人： Douglas A. Pike, Jr. , Dah W. Tsang , James M. Katana
IPC分类号： H01L21/033 , H01L21/22 , H01L21/266 , H01L21/3065 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/739 , H01L29/745 , H01L29/749 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/033 , H01L21/221 , H01L21/266 , H01L21/3065 , H01L29/0619 , H01L29/1095 , H01L29/408 , H01L29/41741 , H01L29/41766 , H01L29/6634 , H01L29/66545 , H01L29/7396 , H01L29/7455 , H01L29/749 , Y10S438/904 , Y10S438/917
摘要： For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay. P+ doping beneath and marginally surrounding the gate pads and main gate bus negates breakdown conditions in widely spaced body regions and convex localities at the source finger end. Wide secondary gate buses parallel to the gate fingers have a P+ doped central stripe and transverse shorting bars spaced along their length. A non-polarizable PECVD passivation film of low phosphorus PSG and nitride or oxynitride or of oxynitride alone is made by controlling ionized gas residence time, silane partial pressure, and oxygen ratio during deposition, to minimize incorporation of Si-H into the film.

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