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1. 发明授权

US08912103B2 Method of fabricating and correcting nanoimprint lithography templates 有权
标题翻译：纳米压印光刻模板的制作和修正方法
公开(公告)号：US08912103B2
公开(公告)日：2014-12-16
申请号：US13681468
申请日：2012-11-20
申请人： Samsung Electronics Co., Ltd.
发明人： Jin-Seok Heo , Jeong-Ho Yeo
IPC分类号： H01L21/00 , H01L21/308 , H01L21/027 , B82Y10/00 , G03F7/00
CPC分类号： H01L21/3086 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/0271 , H01L21/0273 , Y10S438/942 , Y10T29/49
摘要： A method of fabricating a nanoimprint lithography template includes installing a reticle on a reticle stage of scanning lithography equipment having a light source, the reticle stage and a template stage, mounting a template substrate on the template stage, and scanning the template substrate with light from the light source in an exposure process in which the light passes through the reticle and impinges the template substrate at an oblique angle of incidence.
摘要翻译：制造纳米压印光刻模板的方法包括在具有光源，标线片台和模板台的扫描光刻设备的标线片平台上安装掩模版，在模板台上安装模板基板，并用来自曝光过程中的光源，其中光通过掩模版并以倾斜的入射角撞击模板基板。

2. 发明授权

US08828748B2 Test structures and methods 有权
标题翻译：测试结构和方法
公开(公告)号：US08828748B2
公开(公告)日：2014-09-09
申请号：US13902412
申请日：2013-05-24
申请人： Infineon Technologies AG
发明人： Sajan Marokkey
IPC分类号： H01L21/00 , H04R31/00 , G01N21/956 , H02N99/00 , H04R7/10 , H01J37/26
CPC分类号： H02N99/00 , G01N21/956 , G03F1/26 , G03F1/32 , G03F1/44 , G03F1/70 , G03F7/70558 , G03F7/70625 , G03F7/70641 , H01J37/26 , H01L22/12 , H04R7/10 , H04R31/003 , Y10S438/942
摘要： Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece.
摘要翻译：公开了用于半导体器件，光刻系统和光刻工艺的测试结构和方法。在一个实施例中，制造半导体器件的方法包括使用光刻系统通过光刻掩模将工件的感光材料层暴露于能量，光刻掩模包括多个具有第一相移的第一测试图案至少一个具有至少一个第二相移的第二测试图案。显影工件的感光材料层，测量从多个第一测试图案和至少多个第二测试图案形成在感光材料层上的特征，以确定最佳聚焦水平或最佳剂量用于曝光工件感光材料层的光刻系统。

3. 发明授权

US08772166B2 Spacer process for on pitch contacts and related structures 有权
标题翻译：间距接触和相关结构的间隔过程
公开(公告)号：US08772166B2
公开(公告)日：2014-07-08
申请号：US13526792
申请日：2012-06-19
申请人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
发明人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
IPC分类号： H01L21/311
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L23/528 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.
摘要翻译：公开了包括用于增加集成电路中的隔离特征的密度的方法。还公开了相关联的结构。在一些实施例中，触点是与其他结构形成的，例如可以由间距倍增形成的导电互连。为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。在可选择定义的材料中的特征被修整，并且间隔物材料被毯子沉积在特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。去除可选择定义的材料，留下由间隔物材料限定的掩模。由间隔物材料限定的图案可以转移到基底上，以形成间距接触。在一些实施例中，上电触点可用于电接触衬底中的导电互连。

4. 发明授权

US08770143B2 Multi-region processing system 有权
标题翻译：多区域处理系统
公开(公告)号：US08770143B2
公开(公告)日：2014-07-08
申请号：US13106059
申请日：2011-05-12
申请人： Rick Endo , Kurt Weiner , Indranil De , James Tsung , Maosheng Zhao
发明人： Rick Endo , Kurt Weiner , Indranil De , James Tsung , Maosheng Zhao
IPC分类号： C23C16/00 , C23C16/50 , B05B1/28 , B05D1/10 , B05D1/00 , B05D3/00 , H05H1/24 , C23F1/00 , H01L21/306 , C25B11/00 , B05B15/04 , B05B15/12
CPC分类号： C23C16/45565 , B05B14/30 , B05B16/80 , B05D1/10 , B05D1/62 , C23C16/4412 , C23C16/45589 , C23C16/4584 , C23C16/4585 , C23C16/4587 , C23C16/50 , Y10S438/942
摘要： The various embodiments of the invention provide for relative movement of the substrate and a process head to access the entire wafer in a minimal space to conduct combinatorial processing on various regions of the substrate. The heads enable site isolated processing within the chamber described and method of using the same are described.
摘要翻译：本发明的各种实施例提供了基板和工艺头在最小空间中访问整个晶片的相对运动，以对基板的各个区域进行组合处理。这些头使得所描述的室内的现场隔离处理和使用其的方法被描述。

5. 发明授权

US08558385B2 Interconnection architecture for semiconductor device 有权
标题翻译：半导体器件互连架构
公开(公告)号：US08558385B2
公开(公告)日：2013-10-15
申请号：US13200359
申请日：2011-09-23
申请人： Jaeman Yoon , Yungi Kim , Kangyoon Lee , Youngwoong Son
发明人： Jaeman Yoon , Yungi Kim , Kangyoon Lee , Youngwoong Son
IPC分类号： H01L23/48
CPC分类号： H01L21/76838 , H01L21/32139 , H01L21/743 , H01L23/522 , H01L27/0203 , H01L27/105 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： An interconnection architecture, for a semiconductor device (having regions arranged to include at least an inner region, an intermediate region located at least aside the inner region, and an outer region located at least on a side of the intermediate region opposite to the inner region, includes: one or more pairs of first and second signal lines, each pair extending from the inner region into the intermediate region; first portions and second portions of the first and second signal lines being parallel, respectively, the first portions being located in the inner region; the first and second portion of at least the first signal line not being collinear; and an intra-pair line-spacing, d(i), for each pair including the following magnitudes, d2 in the inner region, and d2′ in the intermediate region, where d2
摘要翻译：一种互连结构，用于半导体器件（具有至少包括内部区域，至少包括内部区域的中间区域和至少位于与内部区域相对的中间区域的一侧的外部区域的区域）包括：一对或多对第一和第二信号线，每对从内部区域延伸到中间区域;第一和第二信号线的第一部分和第二部分分别平行，第一部分位于内部区域;至少第一信号线的第一和第二部分不是共线的;以及对于包括内部区域中的以下量值d2的每对的对内线间距d（i），以及d2' 在中间区域，其中d2

6. 发明授权

US08507961B2 Solid-state imaging device 有权
标题翻译：固态成像装置
公开(公告)号：US08507961B2
公开(公告)日：2013-08-13
申请号：US11366296
申请日：2006-03-02
申请人： Noriko Takagi , Hiroyuki Mori
发明人： Noriko Takagi , Hiroyuki Mori
IPC分类号： H01L31/062
CPC分类号： H01L27/14643 , H01L27/14603 , H01L27/14609 , H01L27/14612 , H01L27/14689 , H01L31/02 , Y10S438/942
摘要： A solid-state imaging device has improved operating characteristics including a greater withstand voltage and a decrease in the operational noise for the transistors of the device. The solid-state imaging device includes at least a photoelectric converting portion and a plurality of field effect transistors, preferably a thickness of a gate insulating film for the readout and amplifier transistors are different than gate thicknesses of other transistors.
摘要翻译：固态成像器件具有改进的操作特性，包括较高的耐受电压和器件晶体管的工作噪声的降低。固态成像装置至少包括光电转换部分和多个场效应晶体管，优选用于读出和放大晶体管的栅极绝缘膜的厚度不同于其它晶体管的栅极厚度。

7. 发明授权

US08309966B2 Gate driver on array of a display 有权
标题翻译：显示器阵列上的Gate驱动程序
公开(公告)号：US08309966B2
公开(公告)日：2012-11-13
申请号：US12898727
申请日：2010-10-06
申请人： Tung-Chang Tsai , Lee-Hsun Chang , Ming-Chang Shih , Jing-Ru Chen , Kuei-Sheng Tseng
发明人： Tung-Chang Tsai , Lee-Hsun Chang , Ming-Chang Shih , Jing-Ru Chen , Kuei-Sheng Tseng
IPC分类号： H01L29/786
CPC分类号： H01L27/1288 , H01L27/1214 , Y10S438/942
摘要： A gate driver on array of a display includes a substrate having a peripheral region, and a gate driver on array structure formed in the peripheral region. The gate driver on array structure includes a pull-down transistor, and the pull-down transistor has a gate electrode, an insulating layer, a semiconductor island, a source electrode, and a drain electrode. The semiconductor island extends out of both edges of the gate electrode, and extends out of an edge of the source electrode and an edge of the drain electrode.
摘要翻译：显示器阵列上的栅极驱动器包括具有外围区域的基板和形成在周边区域中的阵列结构上的栅极驱动器。阵列结构上的栅极驱动器包括下拉晶体管，并且下拉晶体管具有栅电极，绝缘层，半导体岛，源电极和漏电极。半导体岛从栅电极的两个边缘延伸出来，并延伸出源电极的边缘和漏电极的边缘。

8. 发明授权

US08269221B2 Structure and method for thin film device 有权
标题翻译：薄膜器件的结构和方法
公开(公告)号：US08269221B2
公开(公告)日：2012-09-18
申请号：US12011440
申请日：2008-01-24
申请人： Ping Mei , Albert Jeans , Carl Taussig
发明人： Ping Mei , Albert Jeans , Carl Taussig
IPC分类号： H01L29/786
CPC分类号： H01L29/42384 , H01L29/6675 , H01L29/78645 , H01L29/7869 , Y10S438/942
摘要： Provided is a thin film device and an associated method of making a thin film device. For example, a thin film transistor with nano-gaps in the gate electrode. The method involves providing a substrate. Upon the substrate are then provided a plurality of parallel spaced electrically conductive strips. A plurality of thin film device layers are then deposited upon the conductive strips. A 3D structure is provided upon the plurality of thin film device layers, the structure having a plurality of different heights. The 3D structure and the plurality of thin film device layers are then etched to define a thin film device, such as for example a thin film transistor that is disposed above at least a portion of the conductive strips.
摘要翻译：本发明提供一种制造薄膜器件的薄膜器件和相关方法。例如，在栅电极中具有纳米间隙的薄膜晶体管。该方法包括提供基底。然后在衬底上设置多个平行隔开的导电条。然后将多个薄膜器件层沉积在导电条上。 3D结构设置在多个薄膜器件层上，该结构具有多个不同的高度。然后蚀刻3D结构和多个薄膜器件层以限定薄膜器件，例如设置在至少一部分导电条上的薄膜晶体管。

9. 发明授权

US08263485B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08263485B2
公开(公告)日：2012-09-11
申请号：US13100197
申请日：2011-05-03
申请人： Jin-Ki Jung
发明人： Jin-Ki Jung
IPC分类号： H01L21/3205 , H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/823842 , H01L21/82385 , H01L27/1052 , Y10S438/942
摘要： A method for fabricating semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region.
摘要翻译：一种用于制造半导体器件的方法包括在包括单元区域和外围区域的衬底上形成蚀刻目标层，在单元区域中的蚀刻目标层上形成具有第一部分和第二部分的第一掩模图案，并形成第二掩模图案，其具有在周边区域中的蚀刻目标层上的第一部分和第二部分，在单元区域上形成光致抗蚀剂图案，修剪第二掩模图案的第一部分，去除光致抗蚀剂图案和第一部分的第一部分掩模图案和第二掩模图案的第二部分，并且蚀刻蚀刻目标层以在单元区域中形成图案，并且在周边区域中形成图案。

10. 发明授权

US08247332B2 Hardmask materials 有权
公开(公告)号：US08247332B2
公开(公告)日：2012-08-21
申请号：US12631691
申请日：2009-12-04
申请人： Vishwanathan Rangarajan , George Andrew Antonelli , Ananda Banerji , Bart van Schravendijk
发明人： Vishwanathan Rangarajan , George Andrew Antonelli , Ananda Banerji , Bart van Schravendijk
IPC分类号： H01L21/311 , H01L21/461 , H01L21/469
CPC分类号： H01L21/02274 , C23C16/30 , C23C16/325 , C23C16/34 , C23C16/505 , C23C16/56 , H01J37/32091 , H01J37/32165 , H01L21/02112 , H01L21/02167 , H01L21/022 , H01L21/0332 , H01L21/31144 , H01L21/3148 , H01L21/318 , H01L21/32139 , H01L21/67017 , H01L21/76813 , Y10S438/932 , Y10S438/942
摘要： Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

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