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1. 发明公开

US20240210509A1 SENSOR CIRCUITS, ELECTRONIC DEVICES, AND METHODS FOR PERFORMING INTERNAL CALIBRATION OPERATIONS 审中-公开
公开(公告)号：US20240210509A1
公开(公告)日：2024-06-27
申请号：US18193462
申请日：2023-03-30
申请人： SK hynix Inc.
发明人： Dong Hyun HWANG , Se Won LEE
IPC分类号： G01R35/00 , G01R31/28 , G01R31/316
CPC分类号： G01R35/005 , G01R31/2829 , G01R31/316
摘要： A sensor circuit includes a sensing voltage generating circuit configured to generate a sensing voltage set to have a voltage level corresponding to a sensing condition. The sensor circuit also includes a comparison signal generating circuit configured to compare the sensing voltage with at least one reference voltage to generate at least one comparison signal. The sensor circuit further includes a voltage code calibrating circuit configured to calibrate at least one voltage code for adjusting a voltage level of the reference voltage, based on the at least one comparison signal.

2. 发明授权

US11409933B2 Method for diagnosing analog circuit fault based on cross wavelet features 有权
公开(公告)号：US11409933B2
公开(公告)日：2022-08-09
申请号：US16762926
申请日：2017-12-07
申请人： HEFEI UNIVERSITY OF TECHNOLOGY
发明人： Yigang He , Wei He , Zhigang Li , Lei Zuo , Bing Li , Liulu He
IPC分类号： G06F30/367 , G01R31/316
摘要： A method for diagnosing analog circuit fault based on cross wavelet features includes steps of: inputting an excitation signal to an analog circuit under test, and collecting time domain response output signals to form an original data sample set; dividing the original data sample set into a training sample set and a test sample set; performing cross wavelet decomposition on both sets; applying bidirectional two-dimensional linear discriminant analysis to process the wavelet cross spectra of the training sample set and the test sample set, and extracting fault feature vectors of the training sample set and the test sample set; submitting the fault feature vectors of the training sample set to a support vector machine for training an SVM classifier, constructing a support vector machine fault diagnosis model; and inputting the fault feature vectors of the test sample set into the model to perform fault classification.

3. 发明授权

US11002789B2 Analog circuit fault feature extraction method based on parameter random distribution neighbor embedding winner-take-all method 有权
公开(公告)号：US11002789B2
公开(公告)日：2021-05-11
申请号：US16166071
申请日：2018-10-20
申请人： WUHAN UNIVERSITY
发明人： Yigang He , Wei He , Hui Zhang , Liulu He , Baiqiang Yin , Bing Li
IPC分类号： G01R31/316 , G06F17/14
摘要： An analog circuit fault feature extraction method based on a parameter random distribution neighbor embedding winner-take-all method, comprising the following steps: (1) collecting a time-domain response signal of an analog circuit under test, wherein the input of the analog circuit under test is excited by using a pulse signal, a voltage signal is sampled at an output end, and the collected time-domain response signal is an output voltage signal of the analog circuit; (2) applying a discrete wavelet packet transform for the collected time-domain response signal to acquire each wavelet node signal; (3) calculating energy values and kurtosis values of the acquired wavelet node signals to form an initial fault feature data set of the analog circuit; and (4) analyzing the initial fault feature data by the parameter random distribution neighbor embedding winner-take-all method, to acquire optimum low-dimensional feature data. The invention effectively reduces redundancy and interference elements in the fault features, and greatly improves degree of separation of different fault features and degree of polymerization of samples of same fault category.

4. 发明申请

US20200274289A1 HIGH VOLTAGE INTERLOCK CIRCUIT AND DETECTION METHOD 审中-公开
公开(公告)号：US20200274289A1
公开(公告)日：2020-08-27
申请号：US16798365
申请日：2020-02-22
申请人： Contemporary Amperex Technology Co., Limited
发明人： Jinglin Li , Jianwei Zhuo , Changjian Liu , Qiandeng Li
IPC分类号： H01R13/53 , G01R31/316 , B60L50/16 , H01R13/70 , H01R13/66
摘要： The disclosure provides high voltage interlock circuit and detection method. The circuit comprises: a power module, a positive electrode of the power module being connected to one end of a current generating module; the current generating module, the other end of the current generating module being connected to a first terminal of a high voltage component module to inject a constant DC current into the high voltage component module; a first voltage dividing module, one end of the first voltage dividing module being connected to a second terminal of the high voltage component module, and the other end of the first voltage dividing module being connected to a negative electrode of the power module and a power ground; and a processing module to determine a fault of the high voltage component module based on a first voltage collected from the second terminal of the high voltage component module.

5. 发明申请

US20180292457A1 Method and Device for Analyzing an Electrical Circuit 审中-公开
公开(公告)号：US20180292457A1
公开(公告)日：2018-10-11
申请号：US15672324
申请日：2017-08-09
申请人： Wistron NeWeb Corporation
发明人： Yuan-Chia Hsu
IPC分类号： G01R31/319 , G01R27/26 , G01R31/317 , G01R31/02 , G01R31/316 , H04B17/23
摘要： A method of analyzing an electrical circuit applied for an electrical system is disclosed. The method includes steps of obtaining a loss parameter and an eye diagram of a circuit channel of the electrical system; comparing the eye diagram with a standard eye diagram to generate a comparison result; generating an analytic result of the loss parameter according to the comparison result in order to adjust the eye diagram; and adjusting the loss parameter according to the analytic result.

6. 发明申请

US20180039865A1 ANALOG CIRCUIT FAULT MODE CLASSIFICATION METHOD 审中-公开
公开(公告)号：US20180039865A1
公开(公告)日：2018-02-08
申请号：US15555077
申请日：2015-11-24
申请人： HEFEI UNIVERSITY OF TECHNOLOGY
发明人： Lifen YUAN , Shuai LUO , Yigang HE , Peng CHEN , Chaolong ZHANG , Ying LONG , Zhen CHENG , Zhijie YUAN , Deqin ZHAO
IPC分类号： G06K9/62 , G06K9/03 , G01R31/316 , G06K9/00
摘要： An analog circuit fault mode classification method comprises the following implementation steps: (1) collecting M groups of voltage signal sample vectors Vij to each of fault modes Fi of the analog circuit by using a data collection board; (2) sequentially extracting fault characteristic vectors VijF of the voltage signal sample vectors Vij by using subspace projection; (3) standardizing the extracted fault characteristic vectors VijF to obtain standardized fault characteristic vectors; (4) constructing a fault mode classifier based on a support vector machine, inputting the standardized fault characteristic vectors, performing learning and training on the classifier, and determining structure parameters of the classifier; and (5) completing determination of fault modes according to fault mode determination rules. The fault mode classifier of the present invention is simple in learning and training and reliable in mode classification accuracy.

7. 发明申请

US20140197868A1 DRIVING CIRCUIT HAVING BUILT-IN-SELF-TEST FUNCTION 有权
标题翻译：具有内置自检功能的驱动电路
公开(公告)号：US20140197868A1
公开(公告)日：2014-07-17
申请号：US14157165
申请日：2014-01-16
申请人： Raydium Semiconductor Corporation
发明人： Chih-Chuan Huang , Ko-Yang Tso
IPC分类号： G01R31/316
CPC分类号： G09G3/006 , G09G3/36
摘要： A driving circuit includes at least one reference voltage source, at least one offset unit, and at least one buffer module. The at least one reference voltage source generates a reference voltage. The at least one offset unit generates an offset voltage, wherein the offset voltage and the reference voltage form a judging voltage range. The at least one buffer module has a first input end, a second input end, and an output end, wherein the first input end receives an analog voltage; the at least one reference voltage source is connected with the second input end; the at least one buffer module, according as whether the analog voltage is within the judging voltage range, outputs a pass logic signal or a fail logic signal at the output end. Particularly, the buffer module has Built-In-Self-Test (BIST) function and can increase test efficiency and voltage accuracy.
摘要翻译：驱动电路包括至少一个参考电压源，至少一个偏移单元和至少一个缓冲模块。至少一个参考电压源产生参考电压。所述至少一个偏移单元产生偏移电压，其中所述偏移电压和所述参考电压形成判定电压范围。所述至少一个缓冲器模块具有第一输入端，第二输入端和输出端，其中所述第一输入端接收模拟电压; 所述至少一个参考电压源与所述第二输入端连接; 所述至少一个缓冲器模块根据模拟电压是否在判定电压范围内，在输出端输出通过逻辑信号或故障逻辑信号。特别地，缓冲模块具有内置自检（BIST）功能，可提高测试效率和电压精度。

8. 发明申请

US20120299578A1 Safety switching device for setting a safety-related device to a safe state 有权
公开(公告)号：US20120299578A1
公开(公告)日：2012-11-29
申请号：US13555293
申请日：2012-07-23
申请人： Andre Korrek
发明人： Andre Korrek
IPC分类号： G01R31/316
CPC分类号： G05B9/02 , H01H9/542 , H01H47/002 , H01H51/005 , H02P23/24 , H03M1/12 , H03M1/207
摘要： A safety switching device, with which a safety-related device, can be set into a safe state. The safety switching device has a microprocessor or microcontroller, which can set an electric drive to be protected into a safe state both if an emergency circuit breaker, protective door switch, and/or two-hand switch is activated and also if there is faulty operation of the safety-related device or electric drive. For this purpose, the microprocessor is implemented such that it can determine from at least one analog signal to be measured whether a predetermined parameter lies outside a predetermined operating range. In addition, the microprocessor can be a component of a safety device which is constructed for multiple-channel control of a safety-related electric drive. In this way, the safety switching device can respond to several safety functions independent of each other in order to set an electric drive into a safe state.

9. 发明授权

US07360133B2 Method for creating a JTAG tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool 失效
标题翻译：在切片中创建JTAG抽头控制器的方法，以便在自定义实例创建期间使用，以避免需要边界扫描合成工具
公开(公告)号：US07360133B2
公开(公告)日：2008-04-15
申请号：US10847691
申请日：2004-05-18
申请人： Saket Goyal , James Ngo
发明人： Saket Goyal , James Ngo
IPC分类号： G01R31/3185 , G01R31/316
CPC分类号： H01L27/118 , G01R31/318555 , G06F17/5045
摘要： A method and system is provided for creating a tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool. Aspects of the present invention include during slice creation, using a software tool to create a test access port (TAP) from slice resources; during instance creation, allowing a customer to design a custom chip using the software tool to select which structures to use on the slice; and based on the customer selections, reconfiguring at the instance level connections between the tap controller and the selected structures.
摘要翻译：提供了一种方法和系统，用于在切片中创建抽头控制器，以在自定义实例创建期间使用，以避免需要边界扫描合成工具。本发明的方面包括在切片创建期间，使用软件工具从切片资源创建测试访问端口（TAP）; 在创建实例期间，允许客户使用软件工具设计定制芯片，以选择在片上使用哪些结构; 并且基于客户选择，在实例级别重新配置抽头控制器和所选结构之间的连接。

10. 发明授权

US07284174B2 Enhanced JTAG interface 有权
标题翻译：增强型JTAG接口
公开(公告)号：US07284174B2
公开(公告)日：2007-10-16
申请号：US11024574
申请日：2004-12-29
申请人： Rohit Dubey
发明人： Rohit Dubey
IPC分类号： G01R31/317 , G01R31/316
CPC分类号： G01R31/318577 , G01R31/318541 , G01R31/318555
摘要： An enhanced JTAG interface provides an additional clock output at any desired I/O port of a logic device during normal operation. The interface includes a boundary scan data cell associated with each I/O port that enables either input data to the I/O port in a normal mode or routes the boundary scan input data during a JTAG operation. A control cell is associated with each data cell for selectively enabling either a normal mode or a JTAG mode of the boundary scan cell. A set of JTAG instructions enable/disable JTAG operation and select JTAG functions. The boundary scan data cell is modified to incorporate a multiplexing arrangement to selectively route the JTAG clock to the I/O port when required. The control cell is modified to selectively enable/disable the routing of the JTAG clock in the boundary scan data cell.
摘要翻译：增强的JTAG接口在正常操作期间在逻辑器件的任何所需I / O端口提供额外的时钟输出。该接口包括与每个I / O端口相关联的边界扫描数据单元，其能够以正常模式输入数据到I / O端口，或者在JTAG操作期间路由边界扫描输入数据。控制单元与每个数据单元相关联，用于选择性地启用边界扫描单元的正常模式或JTAG模式。一组JTAG指令启用/禁用JTAG操作并选择JTAG功能。修改边界扫描数据单元以合并复用布置，以便在需要时选择性地将JTAG时钟路由到I / O端口。修改控制单元以选择性地启用/禁用边界扫描数据单元中JTAG时钟的路由。

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