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1. 发明公开

US20240210509A1 SENSOR CIRCUITS, ELECTRONIC DEVICES, AND METHODS FOR PERFORMING INTERNAL CALIBRATION OPERATIONS 审中-公开
公开(公告)号：US20240210509A1
公开(公告)日：2024-06-27
申请号：US18193462
申请日：2023-03-30
申请人： SK hynix Inc.
发明人： Dong Hyun HWANG , Se Won LEE
IPC分类号： G01R35/00 , G01R31/28 , G01R31/316
CPC分类号： G01R35/005 , G01R31/2829 , G01R31/316
摘要： A sensor circuit includes a sensing voltage generating circuit configured to generate a sensing voltage set to have a voltage level corresponding to a sensing condition. The sensor circuit also includes a comparison signal generating circuit configured to compare the sensing voltage with at least one reference voltage to generate at least one comparison signal. The sensor circuit further includes a voltage code calibrating circuit configured to calibrate at least one voltage code for adjusting a voltage level of the reference voltage, based on the at least one comparison signal.

2. 发明申请

US20100109676A1 ANALOG CIRCUIT TESTING AND TEST PATTERN GENERATION 有权
标题翻译：模拟电路测试和测试模式生成
公开(公告)号：US20100109676A1
公开(公告)日：2010-05-06
申请号：US12594967
申请日：2008-04-03
申请人： Amir Zjajo , Jose De Jesus Pineda De Gyvez , Alexander G. Gronthoud
发明人： Amir Zjajo , Jose De Jesus Pineda De Gyvez , Alexander G. Gronthoud
IPC分类号： G01R31/02
CPC分类号： G01R31/31813 , G01R31/316
摘要： Test vectors for structural testing of an analog circuit are selected by first selecting an initial set of test input vectors for the analog circuit. A set of faults is selected, comprising faults that each correspond to a respective node in the analog circuit and corresponding fault voltage value for that node. A measure of overlap is computed between probability distributions of test output signal values for the analog circuit in response to the test input vectors in the presence and absence of each of the faults from said set of faults respectively, as a function of estimated statistical spread of component and/or process parameter values in the analog circuit. Test input vectors are selected from the initial set of test input vectors for use in testing on the basis of whether the measure of overlap for at least one if the faults is below a threshold value in response to the selected test input vector under control of the test selection computer.
摘要翻译：通过首先选择模拟电路的初始测试输入向量集来选择模拟电路结构测试的测试向量。选择一组故障，其中包括每个对应于模拟电路中的相应节点的故障以及该节点的对应的故障电压值。在模拟电路的测试输出信号值的概率分布中，根据来自所述故障组的每个故障的存在和不存在的测试输入向量，分别计算重叠的度量，作为估计的统计扩展的函数模拟电路中的组件和/或过程参数值。从用于测试的初始测试输入向量组中选择测试输入向量，该测试输入向量基于如果故障低于阈值的至少一个的重叠测量是响应于所选择的测试输入向量在测试选择电脑。

3. 发明授权

US07688058B2 Integrated spectrum analyzer circuits and methods for providing on-chip diagnostics 有权
标题翻译：用于提供片上诊断功能的集成频谱分析仪电路和方法
公开(公告)号：US07688058B2
公开(公告)日：2010-03-30
申请号：US12212247
申请日：2008-09-17
申请人： Keith Aelwyn Jenkins , Anup Paul Jose , Scott Kevin Reynolds
发明人： Keith Aelwyn Jenkins , Anup Paul Jose , Scott Kevin Reynolds
IPC分类号： G01R23/00 , G01R23/14
CPC分类号： G01R23/16 , G01R23/20 , G01R31/316 , G01R31/3167
摘要： Spectrum analyzer circuits and methods are provided which implement “zero-IF” (direct conversion) or “near-zero IF” (or very low IF) architectures that enable implementation of integrated (on-chip) spectrum analyzers for measuring the frequency spectrum of internal chip signals. An integrated spectrum analyzer circuit, which comprises a zero IF or near-zero IF framework, enables a low-power compact design with sufficient resolution bandwidth for on-chip implementation and diagnostics of internal chip signals.
摘要翻译：提供了实现“零中频”（直接转换）或“近零中频”（或非常低的IF）架构的频谱分析仪电路和方法，其能够实现集成（片上）频谱分析仪，用于测量频谱内部芯片信号。包含零中频或近零IF框架的集成频谱分析仪电路实现了低功耗紧凑设计，具有足够的分辨率带宽，用于片内实现和内部芯片信号的诊断。

4. 发明申请

US20080001798A1 Performing a signal analysis based on digital samples in conjunction with analog samples 失效
标题翻译：根据数字样本和模拟样本进行信号分析
公开(公告)号：US20080001798A1
公开(公告)日：2008-01-03
申请号：US11809298
申请日：2007-05-31
申请人： Joachim Moll , Heiko Schmitt , Michael Fleischer-Reumann
发明人： Joachim Moll , Heiko Schmitt , Michael Fleischer-Reumann
IPC分类号： G01R31/3167 , G01R31/28 , H03B21/00
CPC分类号： G01R31/31708 , G01R31/316
摘要： Testing a device under test—DUT—includes providing a test signal from the DUT to a test probe, taking from the test signal being present at the test probe analog samples at a first sampling rate, taking from the test signal being present at the test probe digital samples at a second sampling rate, providing a control signal indicative of sampling times of the analog samples, and performing an analysis of the digital samples in conjunction with the control signal.
摘要翻译：测试被测器件包括从DUT提供测试信号到测试探头，从测试信号以测试信号以第一采样速率从测试探头模拟采样中得到，测试信号取自测试中的测试信号以第二采样率探测数字采样，提供指示模拟采样的采样时间的控制信号，以及结合控制信号执行数字采样的分析。

5. 发明申请

US20070268030A1 Spatial transformer for RF and low current interconnect 失效
标题翻译： RF和低电流互连的空间变压器
公开(公告)号：US20070268030A1
公开(公告)日：2007-11-22
申请号：US11436821
申请日：2006-05-18
申请人： William Knauer , Eric Saint-Etienne , Vincent Reynaud
发明人： William Knauer , Eric Saint-Etienne , Vincent Reynaud
IPC分类号： G01R31/02
CPC分类号： G01R31/2889 , G01R31/316
摘要： A spatial transformer includes an insulating substrate; a plurality of test terminal assemblies on the substrate; and a plurality of contact surfaces on the transformer, each providing an interconnection point for electrical connection between a respective test terminal assembly and a device under test. Each test terminal assembly has a center conductor trace on an upper substrate surface; a lower substrate guard trace beneath the center conductor trace; and a pair of upper substrate guard traces adjacent to opposite sides of the center conductor trace, the guard traces being electrically interconnected. The guard traces in combination with the center conductor trace provide a desired characteristic impedance for an RF signal applied therebetween or a guarded DC connection for a DC signal applied to the center conductor trace and a DC guard applied to the guard traces.
摘要翻译：空间变压器包括绝缘衬底; 在基板上的多个测试端子组件; 以及变压器上的多个接触表面，每个提供用于相应测试端子组件和被测器件之间的电连接的互连点。每个测试端子组件在上基板表面上具有中心导体迹线; 在中心导体迹线下面的下基板保护迹线; 以及与中心导体迹线的相对侧相邻的一对上基板保护迹线，保护迹线电互连。与中心导体迹线组合的保护迹线为施加在其间的RF信号提供期望的特性阻抗，或者对施加到中心导体迹线的DC信号的保护DC连接以及施加到保护迹线的DC保护。

6. 发明申请

US20070230513A1 TRANSMITTER VOLTAGE AND RECEIVER TIME MARGINING 有权
标题翻译：发射器电压和接收器时间限制
公开(公告)号：US20070230513A1
公开(公告)日：2007-10-04
申请号：US11668010
申请日：2007-01-29
申请人： Gerald R. Talbot , Paul C. Miranda , Emerson S. Fang , Rohit Kumar
发明人： Gerald R. Talbot , Paul C. Miranda , Emerson S. Fang , Rohit Kumar
IPC分类号： H04J3/06
CPC分类号： G01R31/30 , G01R31/3004 , G01R31/316 , G01R31/317 , H04L1/20 , H04L7/0337
摘要： A technique for characterizing a communications interface includes determining a voltage margin and a timing margin of the interface based on data sampled by a sampling device of a receiver of the interface. In at least one embodiment of the invention, a method for determining margin associated with a receiver circuit of an integrated circuit includes periodically sampling a signal over a time period by a receiver sampling circuit of the receiver circuit to generate a sampled version of the signal. The method includes incrementally varying a value of the parameter associated with the signal. The varying of the parameter is through a range of values of the parameter over the time period. The method includes determining a margin value of the receiver circuit associated with the parameter based, at least in part, on the sampled version of the signal.
摘要翻译：用于表征通信接口的技术包括基于由接口的接收机的采样设备采样的数据来确定接口的电压余量和定时裕度。在本发明的至少一个实施例中，用于确定与集成电路的接收机电路相关联的裕量的方法包括由接收机电路的接收机采样电路在一段时间周期性地对信号进行采样以产生信号的采样版本。该方法包括递增地改变与信号相关联的参数的值。参数的变化是通过该时间段内参数值的范围。该方法包括至少部分地基于信号的采样版本来确定与参数相关联的接收机电路的边缘值。

7. 发明申请

US20070004042A1 Compositions and methods for helper-free production of recombinant adeno-associated viruses 审中-公开
标题翻译：无辅助生产重组腺相关病毒的组合物和方法
公开(公告)号：US20070004042A1
公开(公告)日：2007-01-04
申请号：US11397324
申请日：2006-04-04
申请人： Guangping Gao , James Wilson
发明人： Guangping Gao , James Wilson
IPC分类号： C12N15/861 , C12N5/06
CPC分类号： G01R31/275 , C12N15/86 , C12N2710/10344 , C12N2750/14143 , C12N2750/14151 , C12N2840/20 , G01R31/013 , G01R31/316
摘要： A method for producing recombinant adeno-associated virus in the absence of contaminating helper virus or wild-type virus involves culturing a mammalian host cell containing an rAd/AAV hybrid virus, an AAV rep sequence and an AAV cap sequence under the control of regulatory sequences directing expression thereof. The rAd/AAV hybrid virus contains a rAAV construct to be packaged into an AAV virion in a backbone containing the adenoviral sequences necessary to express E1a and E1b gene products and to permit replication of the hybrid virus. The method of the invention permits replication of the hybrid virus and production of rAAV virion in this host cell in the absence of a helper virus and obviates a subsequent purification step to purify rAAV from contaminating virus.
摘要翻译：在不存在污染性辅助病毒或野生型病毒的情况下用于产生重组腺相关病毒的方法包括在调节序列的控制下培养含有rAd / AAV杂合病毒，AAV rep序列和AAV帽序列的哺乳动物宿主细胞指导其表达。 rAd / AAV杂合病毒含有一个rAAV构建体，其被包装在含有表达E1a和E1b基因产物所必需的腺病毒序列并且允许杂交病毒复制的骨架中的AAV病毒粒子中。本发明的方法允许在不存在辅助病毒的情况下复制该杂种病毒并在该宿主细胞中产生rAAV病毒粒子，并且消除随后的纯化步骤以从污染病毒纯化rAAV。

8. 发明申请

US20060025946A1 Integrated spectrum analyzer circuits and methods for providing on-chip diagnostics 失效
标题翻译：用于提供片上诊断功能的集成频谱分析仪电路和方法
公开(公告)号：US20060025946A1
公开(公告)日：2006-02-02
申请号：US10900733
申请日：2004-07-28
申请人： Keith Jenkins , Anup Jose , Scott Reynolds
发明人： Keith Jenkins , Anup Jose , Scott Reynolds
IPC分类号： G01R23/16
CPC分类号： G01R23/16 , G01R23/20 , G01R31/316 , G01R31/3167
摘要： Spectrum analyzer circuits and methods are provided which implement “zero-IF” (direct conversion) or “near-zero IF” (or very low IF) architectures that enable implementation of integrated (on-chip) spectrum analyzers for measuring the frequency spectrum of internal chip signals. An integrated spectrum analyzer circuit, which comprises a zero IF or near-zero IF framework, enables a low-power compact design with sufficient resolution bandwidth for on-chip implementation and diagnostics of internal chip signals.
摘要翻译：提供了实现“零中频”（直接转换）或“近零中频”（或非常低的IF）架构的频谱分析仪电路和方法，其能够实现集成（片上）频谱分析仪，用于测量频谱内部芯片信号。包含零中频或近零IF框架的集成频谱分析仪电路实现了低功耗紧凑设计，具有足够的分辨率带宽，用于片内实现和内部芯片信号的诊断。

9. 发明申请

US20050049809A1 Analog circuit automatic calibration system 有权
标题翻译：模拟电路自动校准系统
公开(公告)号：US20050049809A1
公开(公告)日：2005-03-03
申请号：US10915345
申请日：2004-08-11
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
IPC分类号： G01R31/316 , G01R35/00 , G06F19/00
CPC分类号： G01R35/005 , G01R31/316
摘要： An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.
摘要翻译：一种模拟电路自动校准系统，用于校准作为具有随着输入设定值变化的特性的模拟电路的目标电路。该系统包括：设定值存储部分，用于存储值并将该值输出到对象电路作为设定值; 用于检测所述目标电路的特性的特性检测部分; 用于确定所述设定值使得所述对象电路的特性被优化的第一特征变化部分; 第二特征变化部，使用与第一特征变化部中使用的算法不同的算法来更新设定值，使得保持对象电路的特性; 以及选择器，用于选择第一和第二特征部分的输出之一，以使所选择的一个存储在设定值存储部分中。

10. 发明授权

US06724182B2 Tester and testing method for differential data drivers 失效
标题翻译：差分数据驱动程序的测试和测试方法
公开(公告)号：US06724182B2
公开(公告)日：2004-04-20
申请号：US10093536
申请日：2002-03-11
申请人： Koji Isodono , Toyohiko Tanaka , Hitoshi Imai , Hitoshi Saitoh
发明人： Koji Isodono , Toyohiko Tanaka , Hitoshi Imai , Hitoshi Saitoh
IPC分类号： G01R3100
CPC分类号： G01R31/316 , G01R31/31924
摘要： A pair of resistors, having substantially equivalent resistance are arranged in series so that two data output lines of a differential data driver are connected to the ends of the series of resistors, the potentials of the two output signals ((D+)data output signal and (D−)data output signal) from the differential data driver are resistively divided to detect the sum of the potentials of the two signals. Based on the voltage of the combined signal, the acceptability of the differential signals of the differential data driver is determined.
摘要翻译：具有基本上等效电阻的一对电阻器串联布置，使得差分数据驱动器的两条数据输出线连接到一系列电阻器的两端，两个输出信号（（D +）数据输出信号和（D-）数据输出信号）被电阻分压以检测两个信号的电位之和。基于组合信号的电压，确定差分数据驱动器的差分信号的可接受性。

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