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1. 发明授权

US10817367B2 Out-of-bounds recovery circuit 有权
公开(公告)号：US10817367B2
公开(公告)日：2020-10-27
申请号：US15784746
申请日：2017-10-16
申请人： Imagination Technologies Limited
发明人： Ashish Darbari , Iain Singleton
IPC分类号： G06F11/00 , G06F11/07 , G06F30/30 , G06F30/392 , G06F115/10 , G06F117/06
摘要： Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

2. 发明授权

US10810345B2 Modifying a manufacturing process of integrated circuits based on large scale quality performance prediction and optimization 有权
公开(公告)号：US10810345B2
公开(公告)日：2020-10-20
申请号：US16386608
申请日：2019-04-17
申请人： International Business Machines Corporation
发明人： Steven B. Gold , Wen Wei Low , Feng Xue , Yvonne Chii Yeo , Jung H. Yoon
IPC分类号： G06F30/398 , G06F30/327 , G11C29/00 , G11C29/44 , H01L21/66 , G06F30/39 , G11C29/04 , G06F111/06 , G06F115/10 , G06F119/18
摘要： A computer-implemented method modifies a manufacturing process for integrated circuits that include memory chips and a memory buffer. One or more processors identify a performance trending estimate of memory chip failures versus memory buffer failures in failed integrated circuits. The processor(s) identify a location and address of each memory chip in the identified failed integrated circuits that has a memory chip failure. The processor(s) identify a wafer location on a wafer die on which each memory buffer that has a memory buffer failure was formed. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, the location and address of each memory chip in the failed integrated circuits, and the wafer location on the wafer die on which each memory buffer that has the memory buffer failure was formed such that a manufacturing process for the integrated circuits is modified based on the FA pareto.

3. 发明授权

US11163927B1 Computer system for designing a process unit 有权
公开(公告)号：US11163927B1
公开(公告)日：2021-11-02
申请号：US17060909
申请日：2020-10-01
申请人： CDE Consultants Limited
发明人： Peter Geoffrey Kauders
IPC分类号： G06F30/31 , G06F30/3308 , G06F30/17 , G06F30/18 , G06F115/10 , G06F30/28 , G06F113/08 , G06F113/14
摘要： A computer system for designing a process unit, the process unit comprising a set of unit operations interconnected by streams. The computer system comprises a stream generator (process simulator) configured to simulate the process unit by modelling the set of unit operations and flow conditions of each of the streams that interconnect the unit operations within the process unit. The stream generator generates physical properties of each of the streams based on their respective generated flow conditions. The computer system further comprises a stream engineering properties module configured to determine stream engineering properties of each of the streams based on their respective flow conditions and generated physical properties. The stream engineering properties define engineering requirements of each of the streams. The computer system further comprises a preliminary engineering system configured to determine engineering information based on the determined stream engineering properties, physical properties of each of the streams and flow conditions of each of the streams, wherein the engineering information comprises: equipment engineering data for each of the unit operations and pipe engineering data for each of the streams. The computer system is configured to design the process unit based on interactively integrating the engineering information with the determined stream engineering properties, flow conditions and generated physical properties of the streams through information channels formed by each stream interconnection between a pair of unit operations.

4. 发明授权

US11030039B2 Out-of-bounds recovery circuit 有权
公开(公告)号：US11030039B2
公开(公告)日：2021-06-08
申请号：US17028253
申请日：2020-09-22
申请人： Imagination Technologies Limited
发明人： Ashish Darbari , Iain Singleton
IPC分类号： G06F11/00 , G06F11/07 , G06F30/30 , G06F30/392 , G06F115/10 , G06F117/06
摘要： Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

5. 发明授权

US10803225B2 Peripheral tool 有权
公开(公告)号：US10803225B2
公开(公告)日：2020-10-13
申请号：US16256770
申请日：2019-01-24
申请人： EFINIX, INC.
发明人： James Schleicher
IPC分类号： G06F30/39 , G06F30/392 , G06F30/394 , G06F115/10
摘要： A system having design tools and methods using the same design tools in designing an integrated circuit (IC) are described. In one embodiment, an IC design system comprises, the system comprises one or more processors; and a non-transitory computer readable medium connected to the one or more processors, wherein the non-transitory computer readable medium is configured to store: of a first design tool module configured to determine one or more design specifications for a core of an integrated circuit (IC), the IC comprising a plurality of transistors and other components, and a plurality of interconnects between the plurality of transistors and the other components, wherein the plurality of transistors and the other components and the plurality of interconnects are formed on a single die, and a second design tool configured to determine one or more design specifications for a periphery of the IC, the second design tool module to function independently of the first design tool module and operable to design constraints for interface placement and configuration of an interface between the core and the periphery of the IC.

6. 发明授权

US10740522B1 Apparatus and method of operating timing analysis considering multi-input switching 有权
公开(公告)号：US10740522B1
公开(公告)日：2020-08-11
申请号：US16547497
申请日：2019-08-21
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Moon Su Kim
IPC分类号： G06F17/50 , G06F30/3312 , G06F30/367 , G06F111/10 , G06F115/10 , G06F119/12 , G06F30/398 , G06F30/373
摘要： An apparatus for operation timing analysis of a semiconductor device considering multi-input switching (MIS) includes a timing input unit that generates an MIS model of each of a plurality of cells constituting a semiconductor device, and an MIS analyzer that receives timing data of each of the plurality of cells and dynamically calculates an MIS coefficient on the basis of the MIS model and the timing data.

7. 发明授权

US10671780B2 Information processing device that executes simulation and a simulation method 审中-公开
公开(公告)号：US10671780B2
公开(公告)日：2020-06-02
申请号：US15299509
申请日：2016-10-21
申请人： Fujitsu Limited
发明人： Shinya Kuwamura
IPC分类号： G06F9/44 , G06F30/33 , G06F9/455 , G06F115/10
摘要： A simulation method executable by a computer that executes a simulation of an instruction execution of a program for a target processor, the method including: setting, to be a predicted result, an execution result of processing a memory access instruction; executing a functional simulation of an instruction execution based on an assumption of the predicted result, and obtaining timing information, so as to calculate an execution time for the memory access instruction in the case of the predicted result; generating and executing a host code; determining a type of memory to be accessed in the memory access instruction; and correcting an execution time for the memory access instruction in the case of the predicted result using a value corresponding to a result of determining the type of the memory, so as to obtain an execution time for the memory access instruction in the functional simulation.

8. 发明授权

US11593193B2 Out-of-bounds recovery circuit 有权
公开(公告)号：US11593193B2
公开(公告)日：2023-02-28
申请号：US17338538
申请日：2021-06-03
申请人： Imagination Technologies Limited
发明人： Ashish Darbari , Iain Singleton
IPC分类号： G06F11/07 , G06F21/52 , G06F30/30 , G06F30/392 , G06F115/10 , G06F117/06
摘要： Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

9. 发明授权

US11288429B2 Electrical mask validation 有权
公开(公告)号：US11288429B2
公开(公告)日：2022-03-29
申请号：US16732824
申请日：2020-01-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Daniel Corliss , Derren N. Dunn , Michael A. Guillorn , Shawn P. Fetterolf
IPC分类号： G06F30/34 , H01L23/58 , H01L21/027 , G06F30/36 , G06F30/30 , G06F30/39 , G06F30/333 , G06F115/10 , G06F117/06
摘要： An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

10. 发明授权

US11250197B1 Channel less floor-planning in integrated circuits 有权
公开(公告)号：US11250197B1
公开(公告)日：2022-02-15
申请号：US17079727
申请日：2020-10-26
申请人： QUALCOMM Incorporated
发明人： Vinod Kumar Lakshmipathi , Venugopal Sanaka , Babu Suriamoorthy , Madan Krishnappa , Pavan Kumar Patibanda
IPC分类号： G06F30/30 , G06F30/392 , G06F30/347 , G06F30/394 , G06F115/06 , G06F115/10 , G06F115/02 , G06F119/06
摘要： Various embodiments may include integrated circuits (ICs) and methods for designing an integrated circuit (IC), such as a system-on-chip (SOC). Embodiments include methods for planning and producing ICs without communication channels, also referred to as channel-less ICs. Embodiments may include overlay hard macros that support routing and communication design without dedicated communication channels being needed between functional hard macros, such as cores of a SOC. Various embodiments may include an IC in which one or more interconnect hard macros and wires connecting a first functional hard macro, a second functional hard macro and the one or more interconnect hard macros are located within a third functional hard macro. In some embodiments, no communication channel may be present between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

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