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1. 发明授权

US11023633B2 High-level synthesis method, high-level synthesis apparatus, and high-level synthesis system 有权
公开(公告)号：US11023633B2
公开(公告)日：2021-06-01
申请号：US16820204
申请日：2020-03-16
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Shintaro Imamura
IPC分类号： G06F30/327 , G06F115/02
摘要： Disclosed herein is a method of generating an RTL description that implements any functional safety system. A high-level synthesis method for generating an RTL description in which a functional safety system is inserted by using an operation description defining a functional logic, a high-level synthesis script defining a high-level synthesis constraint, and a functional safety system implementation specification specifying a functional safety system to be inserted in a high-level synthesis process. The high-level synthesis method includes a control data flow graph generation step in which a high-level synthesis unit generates a control data flow graph using the operation description, and a first function safety system insertion processing step in which the high-level synthesis unit inserts the function safety system into the control data flow graph according to the function safety system implementation specification after the control data flow graph generation step.

2. 发明授权

US11017141B2 Method for troubleshooting the program logic of a system of distributed progammable gate arrays 有权
公开(公告)号：US11017141B2
公开(公告)日：2021-05-25
申请号：US16874224
申请日：2020-05-14
申请人： dSPACE digital signal processing and control engineering GmbH
发明人： Heiko Kalte , Dominik Lubeley , Marc Schlenger
IPC分类号： G06F30/38 , G06F30/34 , G06F115/02 , G06F117/02
摘要： A method for troubleshooting the program logic of a computer system. A first logic circuit and a first monitoring circuit, which is communicatively isolated from it, are programmed on a first programmable gate array of the computer system. A second logic circuit and a second monitoring circuit, which is communicatively isolated from it, are programmed on a second programmable gate array of the computer system. After an error has been detected in the program logic of the computer system, a first signal line, which applies a signal from the first logic circuit to a first signal input of the first monitoring circuit, is programmed in the first programmable gate array without changing the first logic circuit, and a second signal line, which applies a signal from the second logic circuit, is programmed in the second programmable gate array without changing the second logic circuit.

3. 发明授权

US11520968B2 Verification platform for system on chip and verification method thereof 有权
公开(公告)号：US11520968B2
公开(公告)日：2022-12-06
申请号：US17363839
申请日：2021-06-30
申请人： MONTAGE LZ TECHNOLOGIES (CHENGDU) CO., LTD.
发明人： Huimin Mao , Shunlin Li
IPC分类号： G06F30/398 , G06F30/33 , G06F30/20 , G06F30/3308 , G06F30/367 , G06F11/00 , G01R31/28 , G06F115/02
摘要： The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: generating, by an Universal Verification Methodology test instance, constrained random parameters and random controls, and storing them to a storage area of a bus function model unit; reading, by a software test instance, the random parameters and the random controls through the central processing unit, and configuring a test of the system on chip; storing execution status information of the software test instance in the storage area; reading, by the Universal Verification Methodology test instance, the execution status information, and adjusting constraint condition for generating random parameters and random controls based on the execution status information to exclude having been tested scenarios, and converting the execution status information into coverage data for coverage analysis.

4. 发明授权

US11514225B2 Verification platform for system on chip and verification method thereof 有权
公开(公告)号：US11514225B2
公开(公告)日：2022-11-29
申请号：US17363653
申请日：2021-06-30
申请人： MONTAGE LZ TECHNOLOGIES (CHENGDU) CO., LTD.
发明人： Huimin Mao , Shunlin Li , Chengqiang Liu
IPC分类号： G06F30/398 , G06F30/3308 , G06F30/20 , G06F30/367 , G06F11/00 , G01R31/28 , G06F115/02
摘要： The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: constructing a simulation verification environment for the system on chip; creating a bus function model unit, and binding the bus function model unit to the same interface at which a central processing unit being connected to the bus; creating an Universal Verification Methodology test instance, and performing the Universal Verification Methodology test instance by the bus function model unit to implement the system on chip test; creating a plurality of software test instances; and compiling the software test instances, and performing the compiled software test instances by the central processing unit to implement the system on chip test.

5. 发明授权

US11250197B1 Channel less floor-planning in integrated circuits 有权
公开(公告)号：US11250197B1
公开(公告)日：2022-02-15
申请号：US17079727
申请日：2020-10-26
申请人： QUALCOMM Incorporated
发明人： Vinod Kumar Lakshmipathi , Venugopal Sanaka , Babu Suriamoorthy , Madan Krishnappa , Pavan Kumar Patibanda
IPC分类号： G06F30/30 , G06F30/392 , G06F30/347 , G06F30/394 , G06F115/06 , G06F115/10 , G06F115/02 , G06F119/06
摘要： Various embodiments may include integrated circuits (ICs) and methods for designing an integrated circuit (IC), such as a system-on-chip (SOC). Embodiments include methods for planning and producing ICs without communication channels, also referred to as channel-less ICs. Embodiments may include overlay hard macros that support routing and communication design without dedicated communication channels being needed between functional hard macros, such as cores of a SOC. Various embodiments may include an IC in which one or more interconnect hard macros and wires connecting a first functional hard macro, a second functional hard macro and the one or more interconnect hard macros are located within a third functional hard macro. In some embodiments, no communication channel may be present between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

6. 发明授权

US11074381B2 Verification of hardware design for data transformation component 有权
公开(公告)号：US11074381B2
公开(公告)日：2021-07-27
申请号：US17065678
申请日：2020-10-08
申请人： Imagination Technologies Limited
发明人： Sam Elliott
IPC分类号： G06F30/30 , G06F30/33 , G06F30/337 , G06F30/3323 , G01R31/3183 , G01R31/00 , G06F30/3308 , G06F115/02 , G06F119/16 , G06F111/12
摘要： A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. For each of the plurality of leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. For each of the one or more parent data transformation components, it is formally verified, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the one or more child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component is configured to produce a specific output transaction with a causal deterministic relationship to the specific input transaction.

7. 发明授权

US11568112B2 System design support apparatus and system design support method 有权
公开(公告)号：US11568112B2
公开(公告)日：2023-01-31
申请号：US16345726
申请日：2017-03-30
申请人： Mitsubishi Electric Corporation
发明人： Yurika Oguri
IPC分类号： G06F30/31 , G06F30/00 , G05B19/05 , G05B19/418 , G06F30/34 , G01R31/3183 , G06F9/455 , G06F111/20 , G06F115/02
摘要： A system design support apparatus generates new user data on the basis of derived user data including: base user data reference information that is information specifying user data to be referred to; and information on an item changed from the user data specified by the base user data reference information and on changed contents. A system design support method includes a step of selecting user data to be used, a step of generating derived user data including: base user data reference information for specifying the selected user data to be used; and information on an item changed from the user data specified by the base user data reference information and on changed contents, and a step of generating new user data on the basis of the derived user data.

8. 发明授权

US11126780B1 Automatic net grouping and routing 有权
公开(公告)号：US11126780B1
公开(公告)日：2021-09-21
申请号：US16680210
申请日：2019-11-11
申请人： Synopsys, Inc.
发明人： Yi-Ting Chung , Kuan-Yu Liao , Shih-Pin Hung , Kaichih Chi , Bing Chen , Chun-Cheng Chi
IPC分类号： G06F30/30 , G06F30/3953 , G06F30/394 , G06F30/3947 , G06F115/02
摘要： Techniques and systems for automatic net grouping and routing are described. Some embodiments can determine a set of net groups by automatically grouping nets that have (1) a same pin count, (2) a pin direction type that is in a predefined set of pin direction types, and (3) a pin order type that is in a predefined set of pin order types. Next, the embodiments can generate routing guidance by performing trunk planning for each net group. The embodiments can then perform detailed routing for each net in each net group by using the routing guidance.

9. 发明申请

US20210133991A1 ARTIFICIAL REALITY SYSTEM USING A MULTISURFACE DISPLAY PROTOCOL TO COMMUNICATE SURFACE DATA 有权
公开(公告)号：US20210133991A1
公开(公告)日：2021-05-06
申请号：US16742744
申请日：2020-01-14
申请人： Facebook Technologies, LLC
发明人： Hideo Tamama , Alok Kumar Mathur , Steve John Clohset
IPC分类号： G06T7/40 , G06F30/30 , G06T15/00 , G06F9/54 , G06T19/00 , G02B27/01 , G06F115/02
摘要： This disclosure describes efficient communication of surface texture data between system on a chip (SOC) integrated circuits. An example system includes a first integrated circuit, and at least one second integrated circuit communicatively coupled to the first integrated circuit by a communication interface. The first integrated circuit, upon determining that surface texture data of a frame to be rendered for display by the second SoC integrated circuit is to be updated, (a) transmits the surface texture data in one or more update packets to the second integrated circuit using the communication interface, and (b) transmits a command to the second integrated circuit indicating that the surface texture data of the frame has been updated using the communication interface. The second integrated circuit, upon receipt of the command, (a) sets a pointer to a location in the display buffer storing the surface texture data of the frame, and (b) renders the surface texture data of the frame for display on a display device.

10. 发明授权

US10860766B1 Compilation flow for a heterogeneous multi-core architecture 有权
公开(公告)号：US10860766B1
公开(公告)日：2020-12-08
申请号：US16420881
申请日：2019-05-23
申请人： Xilinx, Inc.
发明人： Mukund Sivaraman , Shail Aditya Gupta , Akella Sastry , Rishi Surendran , Philip B. James-Roxby , Samuel R. Bayliss , Vinod K. Kathail , Ajit K. Agarwal , Ralph D. Wittig
IPC分类号： G06F30/347 , G06F8/41 , G06F16/901 , G06F30/394 , G06F12/1081 , G06F115/02
摘要： An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

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