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1. 发明授权

US11544435B1 On-the-fly computation of analog mixed-signal (AMS) measurements 有权
公开(公告)号：US11544435B1
公开(公告)日：2023-01-03
申请号：US17353208
申请日：2021-06-21
申请人： Synopsys, Inc.
发明人： Dmitry Korchemny , Ilya Kudryavtsev , Eduard Cerny , Dmitriy Mosheyev
IPC分类号： G06F30/3308 , G06F30/38 , G06F30/327 , G06F30/367 , G06F30/398
摘要： The present disclosure generally relates to an analog mixed-signal (AMS) design verification system. In particular, the present disclosure relates to a system and method for system verification. One example method includes: obtaining an electronic representation of the circuit design; generating at least a portion of a waveform using the electronic representation of the circuit to obtain a first segment of the waveform associated with the circuit; converting, via the one or more processors, one or more measurement functions to code for performing the one or more computations on the first segment of the waveform; performing one or more computations on the first segment of the waveform using the code; and identifying when a behavior of the circuit violates a design specification based on whether a result of the one or more computations meets a threshold.

2. 发明授权

US11501475B2 Graphical representation of electronic circuit operation 有权
公开(公告)号：US11501475B2
公开(公告)日：2022-11-15
申请号：US17330794
申请日：2021-05-26
申请人： Steven F. Hoover
发明人： Steven F. Hoover
IPC分类号： G06T11/20 , G06F30/3308 , G06F30/38
摘要： A system displays a visual representation of the operation of an electronic circuit. The position of graphical elements representing values of signals in the circuit convey information about the operation of the circuit. The visual representation may further depict navigable levels of hierarchy of the electronic circuit.

3. 发明授权

US11487926B2 Integrated circuit with a dynamics-based reconfigurable logic block 有权
公开(公告)号：US11487926B2
公开(公告)日：2022-11-01
申请号：US16326603
申请日：2017-08-29
申请人： NORTH CAROLINA STATE UNIVERSITY
发明人： Behnam Kia , William Ditto , Yaman Dalal , Ravikanth Somsole , Siva Rama Maruthi Ven Donepudi Krishna Sesha Sai , Allen R. Mendes , Akshay Parnami , Robin George
IPC分类号： G06F30/38 , G06F30/373 , G06F30/337 , G06F30/333 , G06F119/12
摘要： A system can include a nonlinear circuit and a voltage decoder. The nonlinear circuit can perform an operation on an input voltage. The operation can be changed. A voltage decoder can be communicatively coupled to the nonlinear circuit for receiving an output voltage from the nonlinear circuit that results from the operation performed on the input voltage. The voltage decoder can compare the output voltage to a threshold voltage and determine a result of the operation.

4. 发明授权

US11354471B2 Automated circuit generation 有权
公开(公告)号：US11354471B2
公开(公告)日：2022-06-07
申请号：US16886432
申请日：2020-05-28
申请人： Celera, Inc.
发明人： Calum MacRae , Karen Mason , John Mason , Richard Philpott
IPC分类号： G06F30/327 , G06F30/392 , G06F30/398 , G06F30/367 , G06F30/38 , G06F30/31 , G06F111/12
摘要： Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

5. 发明授权

US08319757B2 Display apparatus and control method thereof 有权
标题翻译：显示装置及其控制方法
公开(公告)号：US08319757B2
公开(公告)日：2012-11-27
申请号：US12031219
申请日：2008-02-14
申请人： Young-hun Choi
发明人： Young-hun Choi
IPC分类号： G06F30/38
CPC分类号： G09G5/006 , G09G2360/02 , G09G2370/042 , G09G2370/045 , G09G2370/047 , G09G2370/20
摘要： A display apparatus and a control method thereof are provided. The display apparatus is coupled to a video signal supply source through at least one connector. The display apparatus includes: a main storage unit which stores extended display identification data (EDID) therein corresponding to the at least one connector; a temporary storage unit which loads the EDID thereto from the main storage unit; and a controller which loads the EDID stored in the main storage unit to the temporary storage unit if power is supplied, and controls to transmit the EDID corresponding to an EDID requesting signal, among the EDID loaded to the temporary storage unit, through the at least one connector if the EDID requesting signal is received through the at least one connector.
摘要翻译：提供了一种显示装置及其控制方法。显示装置通过至少一个连接器耦合到视频信号提供源。显示装置包括：主存储单元，其在其中存储对应于所述至少一个连接器的扩展显示标识数据（EDID）; 临时存储单元，其从所述主存储单元加载所述EDID; 以及控制器，其将存储在所述主存储单元中的EDID加载到所述临时存储单元，如果提供了电力，则控制器通过至少在所述临时存储单元中加载的EDID中发送与EDID请求信号相对应的EDID 一个连接器，如果通过至少一个连接器接收到EDID请求信号。

6. 发明授权

US11640489B2 Method, apparatus, computer device, and storage medium for automatic design of analog circuits based on tree structure 有权
公开(公告)号：US11640489B2
公开(公告)日：2023-05-02
申请号：US17880015
申请日：2022-08-03
申请人： SOUTHERN UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： Xinming Shi , Xin Yao
IPC分类号： G06F30/367 , G06F30/373 , G06F30/38 , G06F30/27 , G06F30/33 , G06F30/337 , G06F30/398
摘要： A method, apparatus, computer device, and storage medium for automatic design of analog circuits based on tree structure. The method includes: setting the maximum height and growth direction of the tree structure; randomly calling the node from the function node library as the parent node; randomly calling the node from the function node library and the port node library as the child according to the growth direction node; if the child node is a terminal node, generating a tree structure; checking the tree structure, if the tree structure satisfies the preset conditions, obtaining the circuit topology and device parameter that conform to the circuit rules; evolving the circuit topology and device parameter to generate an analog circuit. The embodiments achieve the effect of making the tree structure of the designed analog circuit more reasonable.

7. 发明授权

US11501050B1 Analog mixed-signal assertion-based checker system 有权
公开(公告)号：US11501050B1
公开(公告)日：2022-11-15
申请号：US17176993
申请日：2021-02-16
申请人： Synopsys, Inc.
发明人： Dmitry Korchemny , Eduard R. Cerny , Ilya Kudryavtsev
IPC分类号： G06F119/02 , G06F30/367 , G06F30/38
摘要： A design for an analog mixed-signal (AMS) circuit is accessed. An assertion for verifying the behavior of an analog signal in the AMS circuit is also accessed. The assertion is expressed in an assertion language for AMS circuits. A processor verifies the assertion against the predicted behavior of the analog signal in the AMS circuit. In various embodiments, the assertion language contains predefined classes for assertions in the temporal domain, for assertions in the frequency domain, and for assertions based on functional dependencies of an output analog signal on an input analog signal.

8. 发明授权

US11361134B2 Automated circuit generation 有权
公开(公告)号：US11361134B2
公开(公告)日：2022-06-14
申请号：US16886544
申请日：2020-05-28
申请人： Celera, Inc.
发明人： Karen Mason , John Mason
IPC分类号： G06F30/327 , G06F30/367 , G06F30/38 , G06F30/31 , G06F30/398 , G06F30/392 , G06F111/12
摘要： Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

9. 发明授权

US11334704B1 System, method, and computer program product for mixed signal verification 有权
公开(公告)号：US11334704B1
公开(公告)日：2022-05-17
申请号：US17060263
申请日：2020-10-01
申请人： Cadence Design Systems, Inc.
发明人： Nan Zhang , Chandrashekar L. Chetput , Aaron Mitchell Spratt , Joseph Leo Zielke, Jr. , Rajat Kanti Mitra
IPC分类号： G06F30/398 , G06F30/3308 , G06F30/367 , G06F30/38
摘要： The present disclosure relates to a computer-implemented method for mixed signal design verification. Embodiments may include receiving, using a processor, an electronic circuit design and compiling and elaborating the electronic circuit design. Embodiments may also include simulating the electronic circuit design and updating, during the simulating, a System Verilog User-Defined Resolution function (“SV-UDR”) associated with the electronic circuit design.

10. 发明授权

US11170147B2 Simulation method for use in functional equivalence check 有权
公开(公告)号：US11170147B2
公开(公告)日：2021-11-09
申请号：US16544928
申请日：2019-08-20
申请人： Yangtze Memory Technologies Co., Ltd.
发明人： Lu Liao , Mei Wang , Yueping Li
IPC分类号： G06F30/367 , G06F30/3323 , G06F30/327 , G06F30/38
摘要： A function equivalence check method includes receiving a cell list, receiving an analog constraint of a cell in the cell list, generating the full-coverage input stimuli according to the analog constraint, performing a behavioral-level simulation using the full-coverage input stimuli and according to the behavioral code to generate a behavioral-level simulation result, performing a circuit-level simulation using the full-coverage input stimuli and according to the circuit-level netlist to generate a circuit-level simulation result, and comparing the behavioral-level simulation result and the circuit-level simulation result to generate a comparison report for an analog value auto-comparison.

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