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1. 发明授权

US11294631B2 Full adder cell with improved power efficiency 有权
公开(公告)号：US11294631B2
公开(公告)日：2022-04-05
申请号：US16661888
申请日：2019-10-23
申请人： NVIDIA Corp.
发明人： Ilyas Elkin , Ge Yang , Xi Zhang
IPC分类号： G06F7/509 , G06F7/53 , G06F7/533 , H03K19/21 , G06F7/501 , G06F9/30 , G06F7/575
摘要： An adder circuit that includes an operand input and a second operand input to an XNOR cell. The XNOR cell is configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell transforms the output of the XNOR cell into a carry out signal.

2. 发明申请

US20200371749A1 MULTIPLIER CIRCUIT 审中-公开
公开(公告)号：US20200371749A1
公开(公告)日：2020-11-26
申请号：US16417866
申请日：2019-05-21
申请人： Arm Limited
发明人： Michael Alexander KENNEDY , Neil BURGESS , Zichao XIE , Chiloda Ashan Senarath PATHIRANE
IPC分类号： G06F7/53 , G06F7/509
摘要： A multiplier circuit is described in which sub-products calculated in a first stage of a carry-save adder (CSA) network are output early, processed by applying a processing function, and re-injected into a subsequent stage of the CSA network to add the processed sub-products. This allows a CSA network provided for multiplication operations to be reused for operations which require sub-products to be processed and added, such as floating-point dot product operations performed on floating-point values represented in bfloatl6 format.

3. 发明授权

US10707893B2 Second-order delta-sigma modulator and transmission apparatus 有权
公开(公告)号：US10707893B2
公开(公告)日：2020-07-07
申请号：US16464717
申请日：2017-12-01
申请人： NEC Corporation
发明人： Masaaki Tanio
IPC分类号： H03M3/00 , G06F7/509 , G06F7/544 , H03M1/66 , H04L27/12 , H04L27/36
摘要： A second-order ΔΣ modulator includes a plurality of integrators and a parallel higher-bit processing part, and the parallel higher-bit processing part includes a plurality of addition and determination processing sections. The addition and determination processing section receives first and second carry inputs and first and second state inputs, and outputs a quantized output and first and second state outputs. A first selector selects one set from sets of the first and the second state outputs from the plurality of addition and determination processing sections and outputs the selected set, and a second selector selects one quantized output from the quantized outputs from the plurality of addition and determination processing sections. An output of the first selector is used as a selection control signal for the first and the second selectors.

4. 发明授权

US10528323B2 Circuit for addition of multiple binary numbers 有权
公开(公告)号：US10528323B2
公开(公告)日：2020-01-07
申请号：US16145311
申请日：2018-09-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Manuel Beck , Wilhelm Haller , Ulrich Krauch , Kurt Lind , Friedrich Schroeder
IPC分类号： G06F7/50 , G06F7/509
摘要： A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

5. 发明申请

US20190196787A1 APPARATUS AND METHOD FOR RIGHT SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED DOUBLEWORDS 审中-公开
公开(公告)号：US20190196787A1
公开(公告)日：2019-06-27
申请号：US15850682
申请日：2017-12-21
申请人： Intel Corporation
发明人： VENKATESWARA MADDURI , ELMOUSTAPHA OULD-AHMED-VALL , MARK CHARNEY , ROBERT VALENTINE , JESUS CORBAL
IPC分类号： G06F7/509 , G06F9/30
CPC分类号： G06F7/5095 , G06F9/30101 , G06F9/30145
摘要： An apparatus and method for performing sum of absolute differences with accumulation. For example, one embodiment of a processor comprises: a decoder to decode an instruction to generate a decoded instruction; a first source register to store a first plurality of packed bytes; a second source register to store a second plurality of packed bytes; execution circuitry to execute the decoded instruction, the execution circuitry comprising: adder circuitry to determine a difference between each byte in the first source register and a corresponding byte in the second source register, absolute value circuitry to determine an absolute value of each difference, the adder circuitry to add pairs of the absolute values to generate a plurality of temporary results, and extension circuitry to extend the temporary results to temporary words; and accumulator circuitry to add each temporary word to a word from a third source register to generate a plurality of accumulated words; and a destination register to store the accumulated words as packed words.

6. 发明申请

US20190034165A1 CIRCUIT FOR ADDITION OF MULTIPLE BINARY NUMBERS 审中-公开
公开(公告)号：US20190034165A1
公开(公告)日：2019-01-31
申请号：US16145311
申请日：2018-09-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Manuel BECK , Wilhelm HALLER , Ulrich KRAUCH , Kurt LIND , Friedrich SCHROEDER
IPC分类号： G06F7/50 , G06F7/509
CPC分类号： G06F7/50 , G06F7/509
摘要： A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

7. 发明申请

US20160224319A1 HIGH-SPEED THREE-OPERAND N-BIT ADDER 审中-公开
标题翻译：高速三位一体式N位加法器
公开(公告)号：US20160224319A1
公开(公告)日：2016-08-04
申请号：US14610739
申请日：2015-01-30
申请人： Huong HO , Michel Kafrouni
发明人： Huong HO , Michel Kafrouni
IPC分类号： G06F7/509
CPC分类号： G06F7/509
摘要： An adder and a method for calculating a sum of three input operands. The adder comprises a pre-processor, a generator and a post-processor. The pre-processor creates an initial propagation vector having a plurality of bit-positions, each bit-position in the plurality representing whether a carry in bit is propagated as a carry out bit as determined from a value of respective bit-positions of each of the three operands. The pre-processor creates an initial generation vector having a plurality of bit-positions, each bit-position in the plurality representing whether a carry out bit is generated as determined from a value of respective bit-positions of each of the three operands. The generator generates a composite propagation vector and a composite generation vector from parallel prefix operations on the initial propagation vector and initial generation vector. The post-processor calculates the sum from the initial propagation vector, the composite propagation vector and the composite generation vector. The adder has a gate delay of 2 log2(N)+4.
摘要翻译：一种用于计算三个输入操作数之和的加法器和方法。加法器包括预处理器，发生器和后处理器。预处理器创建具有多个位位置的初始传播向量，多个位位置中的每个位位置表示进位位是否作为进位位传播，如从每个的相应位位置的值确定的三个操作数。预处理器创建具有多个比特位置的初始生成向量，多个比特位置表示根据三个操作数中的每一个的相应比特位的值来生成进位比特。生成器从初始传播向量和初始生成向量的并行前缀操作生成复合传播向量和复合生成向量。后处理器计算从初始传播向量，复合传播向量和复合生成向量的和。加法器的门延迟为2log2（N）+4。

8. 发明授权

US09122517B2 Fused multiply-adder with booth-encoding 有权
标题翻译：融合式加法器与展位编码
公开(公告)号：US09122517B2
公开(公告)日：2015-09-01
申请号：US13493002
申请日：2012-06-11
申请人： Maarten J. Boersma , Klaus Michael Kroener , Christophe J. Layer , Silvia M. Mueller
发明人： Maarten J. Boersma , Klaus Michael Kroener , Christophe J. Layer , Silvia M. Mueller
IPC分类号： G06F7/483 , G06F7/53 , G06F7/544 , G06F7/509 , G06F7/533
CPC分类号： G06F7/483 , G06F7/509 , G06F7/5324 , G06F7/5332 , G06F7/5443
摘要： A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.
摘要翻译：公开了一种融合乘法器。融合乘法加法器包括布斯编码器，分数乘法器，进位校正器和加法器。 Booth编码器最初编码第一个操作数。分数乘法器将布斯特编码的第一操作数乘以第二操作数以产生部分乘积，然后将部分乘积减少为一组冗余和和携带向量。进位校正器然后产生用于校正进位矢量的进位校正因子。加法器将冗余和并将载入和进位校正因子加到第三个操作数，以产生最终结果。

9. 发明授权

US08892623B2 Data processing apparatus and method 有权
标题翻译：数据处理装置及方法
公开(公告)号：US08892623B2
公开(公告)日：2014-11-18
申请号：US13523204
申请日：2012-06-14
申请人： Neil Burgess , David Raymond Lutz
发明人： Neil Burgess , David Raymond Lutz
IPC分类号： G06F7/509
CPC分类号： G06F5/01
摘要： Processing circuitry is provided for performing a shift-round-and-accumulate operation. The operation comprises shifting an input value to generate a shifted value using shifting circuitry, adding the shifted value to an accumulate value using adding circuitry, and performing rounding by adding a rounding value to the sum of the shifted value and the accumulated value using the adding circuitry. The same adding circuitry is used to perform both the addition of the shifted value and the accumulated value and the addition of the rounding value in the same processing cycle.
摘要翻译：提供处理电路用于执行移位循环和累加操作。操作包括使用移位电路移位输入值以产生移位值，使用加法电路将移位值加到累加值，并通过使用加法运算加上移位值和累积值的和来进行舍入电路。使用相同的添加电路来执行移位值和累加值的相加以及相同处理周期中舍入值的相加。

10. 发明授权

US5978827A Arithmetic processing 失效
标题翻译：算术处理
公开(公告)号：US5978827A
公开(公告)日：1999-11-02
申请号：US630742
申请日：1996-04-10
申请人： Takeshi Ichikawa
发明人： Takeshi Ichikawa
IPC分类号： G06F7/509 , G06F7/50 , G06F7/52 , G06F7/53 , G06F7/60 , H03K19/23
CPC分类号： G06F7/5318 , G06F7/509 , G06F7/607 , H03K19/23 , G06F2207/3836 , G06F2207/4816 , G06F2207/4822
摘要： In a processor for performing operations including an addition of a plurality of multiple bit data, values on common places of a plurality of multiple bit data are entered in parallel into number detectors set for respective places, the number of the high signals in the input values is output in the binary notation, and outputs from a plurality of NDs are added by full adders to execute a high speed operation without carries. In addition, values with no common places are integrated into single data before being added.
摘要翻译：在用于执行包括多个多位数据的添加的操作的处理器中，将多个多位数据的公共位置上的值并行地输入到为各个位置设置的数字检测器中，输入值中的高信号的数量以二进制符号输出，并且通过全加器添加来自多个ND的输出以执行无携带的高速操作。此外，在添加之前，将没有常见位置的值集成到单个数据中。

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