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1. 发明申请

US20200321239A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20200321239A1
公开(公告)日：2020-10-08
申请号：US16906597
申请日：2020-06-19
申请人： SEIKO EPSON CORPORATION
发明人： Kazunobu KUWAZAWA , Shigeyuki SAKUMA , Hiroaki NITTA , Mitsuo SEKISAWA , Takehiro ENDO
IPC分类号： H01L21/761 , H01L29/735 , H01L29/66 , H01L29/78 , H01L21/8224 , H01L21/8228 , H01L27/092 , H01L27/082 , H01L29/732 , H01L21/225 , H01L27/06 , H01L27/08 , H01L29/06 , H01L29/866 , H01L29/94
摘要： A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.

2. 发明授权

US10714375B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US10714375B2
公开(公告)日：2020-07-14
申请号：US15365790
申请日：2016-11-30
申请人： SEIKO EPSON CORPORATION
发明人： Kazunobu Kuwazawa , Shigeyuki Sakuma , Hiroaki Nitta , Mitsuo Sekisawa , Takehiro Endo
IPC分类号： H01L27/082 , H01L21/761 , H01L29/735 , H01L29/66 , H01L29/78 , H01L21/8224 , H01L21/8228 , H01L27/092 , H01L29/732 , H01L21/225 , H01L27/06 , H01L27/08 , H01L29/06 , H01L29/866 , H01L29/94 , H01L29/10 , H01L29/08 , H01L29/423
摘要： A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.

3. 发明授权

US09337828B2 Transistor including reentrant profile 有权
标题翻译：晶体管包括可重入型材
公开(公告)号：US09337828B2
公开(公告)日：2016-05-10
申请号：US14289678
申请日：2014-05-29
申请人： Lee William Tutt , Shelby Forrester Nelson
发明人： Lee William Tutt , Shelby Forrester Nelson
IPC分类号： H01L21/00 , H01L21/84 , H01L21/8242 , H01L21/8224 , H03K17/687 , H01L29/66 , H01L29/786
CPC分类号： H03K17/687 , H01L29/66787 , H01L29/78642 , H01L29/78681 , H01L29/7869
摘要： A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more of the substrate, the electrically conductive material layer, and the electrically insulating material layer define a reentrant profile.
摘要翻译：晶体管包括衬底，导电材料层和电绝缘材料层。衬底，导电材料层和电绝缘材料层中的一个或多个的至少一部分限定了折入轮廓。

4. 发明授权

US09159816B2 PNP bipolar junction transistor fabrication using selective epitaxy 有权
标题翻译： PNP双极结晶体管制造使用选择性外延
公开(公告)号：US09159816B2
公开(公告)日：2015-10-13
申请号：US14497579
申请日：2014-09-26
申请人： International Business Machines Corporation
发明人： David L. Harame , Qizhi Liu
IPC分类号： H01L29/735 , H01L21/8228 , H01L29/66 , H01L21/8224 , H01L27/082 , H01L29/737 , H01L29/10 , H01L29/06 , H01L29/08 , H01L29/16
CPC分类号： H01L29/735 , H01L21/8224 , H01L21/8228 , H01L27/0821 , H01L29/0649 , H01L29/0808 , H01L29/0826 , H01L29/1004 , H01L29/1008 , H01L29/16 , H01L29/6625 , H01L29/66272 , H01L29/7371
摘要： Lateral PNP bipolar junction transistors and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base.
摘要翻译：横向PNP双极结晶体管和横向PNP双极结晶体管的设计结构。横向PNP双极结晶体管的发射极和集电极由通过选择性外延生长工艺形成的p型半导体材料组成。源极和漏极各自直接接触用于形成发射极和集电极的器件区域的顶表面。基部触点可以形成在顶表面上并且覆盖限定在器件区域内的n型基极。发射极通过基座触点与收集器横向分开。另一个基底接触可以形成在由基部与另一个基部接触分离的器件区域中。

5. 发明授权

US08921194B2 PNP bipolar junction transistor fabrication using selective epitaxy 有权
标题翻译： PNP双极结晶体管制造使用选择性外延
公开(公告)号：US08921194B2
公开(公告)日：2014-12-30
申请号：US13294697
申请日：2011-11-11
申请人： David L. Harame , Qizhi Liu
发明人： David L. Harame , Qizhi Liu
IPC分类号： H01L21/331 , H01L21/8228 , H01L21/8224 , H01L29/66 , H01L27/082 , H01L29/737 , H01L29/10
CPC分类号： H01L29/735 , H01L21/8224 , H01L21/8228 , H01L27/0821 , H01L29/0649 , H01L29/0808 , H01L29/0826 , H01L29/1004 , H01L29/1008 , H01L29/16 , H01L29/6625 , H01L29/66272 , H01L29/7371
摘要： Lateral PNP bipolar junction transistors, methods for fabricating lateral PNP bipolar junction transistors, and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base.
摘要翻译：横向PNP双极结晶体管，用于制造横向PNP双极结型晶体管的方法，以及横向PNP双极结型晶体管的设计结构。横向PNP双极结晶体管的发射极和集电极由通过选择性外延生长工艺形成的p型半导体材料组成。源极和漏极各自直接接触用于形成发射极和集电极的器件区域的顶表面。基部触点可以形成在顶表面上并且覆盖限定在器件区域内的n型基极。发射极通过基座触点与收集器横向分开。另一个基底接触可以形成在由基部与另一个基部接触分离的器件区域中。

6. 发明授权

US08637355B2 Actuating transistor including single layer reentrant profile 有权
标题翻译：驱动晶体管包括单层折入型材
公开(公告)号：US08637355B2
公开(公告)日：2014-01-28
申请号：US13218487
申请日：2011-08-26
申请人： Shelby F. Nelson , Lee W. Tutt
发明人： Shelby F. Nelson , Lee W. Tutt
IPC分类号： H01L21/00 , H01L21/84 , H01L21/8242 , H01L21/8224
CPC分类号： H01L29/78642 , H01L29/41733 , H01L29/66666 , H01L29/78696
摘要： Actuating a semiconductor device includes providing a transistor that includes a substrate and a first electrically conductive material layer, including a reentrant profile, positioned on the substrate. An electrically insulating material layer is conformally positioned over the first electrically conductive material layer and at least a portion of the substrate. A semiconductor material layer conforms to and is in contact with the electrically insulating material layer. A second electrically conductive material layer and third electrically conductive material layer are nonconformally positioned over and in contact with a first portion of the semiconductor material layer and a second portion of the semiconductor material layer, respectively. A voltage is applied between the second electrically conductive material layer and the third electrically conductive material layer and to the first electrically conductive material layer to electrically connect the second and the third electrically conductive material layers.
摘要翻译：激励半导体器件包括提供包括基板和位于基板上的包括凹陷轮廓的第一导电材料层的晶体管。电绝缘材料层保形地定位在第一导电材料层和基板的至少一部分之上。半导体材料层符合并与电绝缘材料层接触。第二导电材料层和第三导电材料层分别不均匀地定位在半导体材料层的第一部分和半导体材料层的第二部分之上并与之接触。在第二导电材料层和第三导电材料层之间以及第一导电材料层上施加电压以电连接第二和第三导电材料层。

7. 发明授权

US08557663B2 Method for manufacturing semiconductor device with vertical gate transistor 失效
标题翻译：具有垂直栅晶体管的半导体器件制造方法
公开(公告)号：US08557663B2
公开(公告)日：2013-10-15
申请号：US13338648
申请日：2011-12-28
申请人： Heung-Jae Cho
发明人： Heung-Jae Cho
IPC分类号： H01L29/732 , H01L21/331 , H01L21/8224
CPC分类号： H01L29/7827 , H01L21/31144 , H01L21/31155 , H01L21/32136 , H01L21/32137 , H01L29/66666
摘要： A method for manufacturing a semiconductor device includes forming a plurality of pillars by etching a semiconductor substrate, forming a gate dielectric layer on sidewalls of the pillars and on surfaces of the semiconductor substrate between the pillars, forming an implant damage in a portion of the gate dielectric layer between two pillars by implanting ions into the portion of the gate dielectric layer, forming vertical gates to cover the sidewalls of the pillars, and removing the implant damage.
摘要翻译：一种用于制造半导体器件的方法包括通过蚀刻半导体衬底形成多个柱，在柱的侧壁上形成栅介质层，并在该柱之间的半导体衬底表面上形成栅极的一部分中的植入物损伤通过将离子注入到栅极电介质层的部分中，形成两个柱之间的介电层，形成垂直栅极以覆盖柱的侧壁，以及去除植入物损伤。

8. 发明申请

US20050269597A1 Complementary analog bipolar transistors with trench-constrained isolation diffusion 有权
公开(公告)号：US20050269597A1
公开(公告)日：2005-12-08
申请号：US11204216
申请日：2005-08-15
申请人： Richard Williams , Michael Cornell , Wai Chan
发明人： Richard Williams , Michael Cornell , Wai Chan
IPC分类号： H01L21/331 , H01L21/76 , H01L21/8222 , H01L21/8224 , H01L21/8228 , H01L21/8234 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/082 , H01L27/088 , H01L29/73 , H01L29/732 , H01L29/739 , H01L31/0328 , H01L31/0336
CPC分类号： H01L27/0826 , H01L21/8224 , H01L21/82285 , H01L27/0821 , H01L29/6625 , H01L29/66272 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa. When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achive deep diffusions with a minimal thermal budget.

9. 发明授权

US6060762A Integrated structure with reduced injection of current between homologous regions 失效
标题翻译：整合结构，减少同源区域之间的电流注入
公开(公告)号：US6060762A
公开(公告)日：2000-05-09
申请号：US855212
申请日：1997-05-13
申请人： Salvatore Scaccianoce , Stefano Sueri
发明人： Salvatore Scaccianoce , Stefano Sueri
IPC分类号： H01L21/8224 , H01L27/082 , H01L29/00
CPC分类号： H01L27/0828 , H01L27/0821
摘要： An integrated semiconductor structure comprises two homologous P-type regions formed within an N-type epitaxial layer. A P-type region formed in the portion of the epitaxial layer disposed between the two P-type regions includes within it an N-type region. This N region is electrically connected to the P region by means of a surface metal contact. The structure reduces the injection of current between the first and second P regions, at the same time preventing any vertical parasitic transistors from being switched on.
摘要翻译：集成半导体结构包括在N型外延层内形成的两个同源P型区。形成在设置在两个P型区域之间的外延层的部分中的P型区域在其内包括N型区域。该N区通过表面金属接触与P区电连接。该结构减少了在第一和第二P区之间的电流注入，同时防止任何垂直寄生晶体管接通。

10. 发明授权

US06005283A Complementary bipolar transistors 失效
标题翻译：互补双极晶体管
公开(公告)号：US06005283A
公开(公告)日：1999-12-21
申请号：US949223
申请日：1997-10-10
申请人： Jong-Hwan Kim , Tae-Hoon Kwon , Cheol-Joong Kim , Suk-Kyun Lee
发明人： Jong-Hwan Kim , Tae-Hoon Kwon , Cheol-Joong Kim , Suk-Kyun Lee
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8224 , H01L21/8226 , H01L21/8228 , H01L27/02 , H01L27/06 , H01L27/08 , H01L27/082 , H01L29/732 , H01L27/102 , H01L29/735
CPC分类号： H01L21/8226 , H01L21/8224 , H01L21/8228 , H01L21/82285 , H01L27/0233 , H01L27/0647 , H01L27/0826
摘要： A complementary bipolar transistor having a lateral npn bipolar trasistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral pnp bipolar transistor has an emitter region and a collector region which includes high-density regions and low-density regions, and the emitter region is formed in an n type tub region. In the integrated injection logic circuit, collector regions are surrounded by a high-density p type region, and low-density p type regions are formed under the collector regions. The diffusion capacitor and the polysilicon capacitor are formed in one substrate. The diffusion regions except the regions formed by diffusing the impurities in the polysilicon resistors into the epitaxial layer are formed before forming the polysilicon resistors, and polysilicon electrodes are formed along with the polysilicon resistors.
摘要翻译：公开了具有横向npn双极性trasistor，垂直和横向pnp双极晶体管，集成注入逻辑，扩散电容器，多晶硅电容器和多晶硅电阻器的互补双极晶体管。横向pnp双极晶体管具有包括高密度区域和低密度区域的发射极区域和集电极区域，并且发射极区域形成在n型槽区域中。在集成注入逻辑电路中，集电极区域被高密度p型区域包围，在集电极区域形成低密度p型区域。扩散电容器和多晶硅电容器形成在一个衬底中。在形成多晶硅电阻器之前形成除了将多晶硅电阻器中的杂质扩散到外延层中形成的区域之外的扩散区域，并且多晶硅电极与多晶硅电阻器一起形成。

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