专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06833332B2 Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same 有权
标题翻译：在硅绝缘体上制造松弛的SiGe缓冲层的方法和含有该SiGe缓冲层的结构
公开(公告)号：US06833332B2
公开(公告)日：2004-12-21
申请号：US10323024
申请日：2002-12-18
申请人： Silke H. Christiansen , Alfred Grill , Patricia M. Mooney
发明人： Silke H. Christiansen , Alfred Grill , Patricia M. Mooney
IPC分类号： H01L2126
CPC分类号： H01L21/76251 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/02631 , H01L21/324 , H01L21/76243
摘要： A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov Ge or SiGe islands on a surface of the SOI substrate; the capping and planarizing of the islands with a Si or Si-rich SiGe layer, and the annealing of the structure at elevated temperatures until intermixing and thereby formation of a relaxed SiGe layer on the insulating layer (i.e., buried oxide layer) of the initial SOI wafer is achieved. The present invention is also directed to semiconductor structures, devices and integrated circuits which include at least the relaxed SiGe buffer layer mentioned above.
摘要翻译：提供了一种在绝缘体上硅（SOI）衬底上制造具有低穿透位错密度的弛豫SiGe缓冲层的方法。通过在SOI衬底的表面上外延沉积无缺陷的Stranski-Krastanov Ge或SiGe岛来制造弛豫的SiGe缓冲层; 用Si或Si富SiGe层对岛进行封盖和平面化，以及在升高的温度下对结构进行退火，直到混合，从而在初始的绝缘层（即，掩埋氧化物层）上形成松弛的SiGe层实现了SOI晶片。本发明还涉及至少包括上述松弛的SiGe缓冲层的半导体结构，器件和集成电路。

2. 发明授权

US06803331B2 Process for the heat treatment of a silicon wafer, and silicon wafer produced 有权
标题翻译：制造硅晶片和硅晶片的热处理工艺
公开(公告)号：US06803331B2
公开(公告)日：2004-10-12
申请号：US10357601
申请日：2003-02-04
申请人： Robert Hölzl , Christoph Seuring , Reinhold Wahlich , Wilfried Von Ammon
发明人： Robert Hölzl , Christoph Seuring , Reinhold Wahlich , Wilfried Von Ammon
IPC分类号： H01L2126
CPC分类号： C30B29/06 , C30B33/00 , H01L21/3225 , H01L21/324 , Y10T117/1088
摘要： A process for the heat treatment of a silicon wafer, during which the silicon wafer is at least temporarily exposed to an oxygen-containing atmosphere, the heat treatment taking place at a temperature which is selected in such a way that the inequality [ Oi ]
摘要翻译：一种用于对硅晶片进行热处理的方法，其中硅晶片至少临时暴露于含氧气氛中，热处理发生在以不等式满足的方式选择的温度下，其中[ Oi]是硅晶片中的氧浓度。（T）是在温度T下氧在硅中的极限溶解度，sigmaSiO 2是二氧化硅的表面能，Ω是沉淀氧原子的体积， r是平均COP半径，k是玻尔兹曼常数。由上述方法制成的硅晶片。

3. 发明授权

US06734119B2 Electro-optical apparatus and method for fabricating a film, semiconductor device and memory device at near atmospheric pressure 有权
标题翻译：电光装置及其制造方法，近似大气压下的半导体装置及记忆装置
公开(公告)号：US06734119B2
公开(公告)日：2004-05-11
申请号：US09778744
申请日：2001-02-08
申请人： Ramesh H. Kakkad
发明人： Ramesh H. Kakkad
IPC分类号： H01L2126
CPC分类号： C23C16/505 , C23C16/482 , H01L21/28556 , H01L21/31612 , H01L21/3185 , H01L29/4908
摘要： A method to deposit insulating, semiconducting, and conducting films at pressures close to the atmospheric pressure and at temperatures less than 500° C. is provided. In this method, noble gas is mixed with reactant gas, and electric energy is applied to produce plasma at pressure substantially close to atmospheric pressure. The process can be applied to deposit films such as silicon dioxide, silicon nitride, silicon, and metal films.
摘要翻译：提供了一种在接近大气压和低于500℃的温度下沉积绝缘，半导体和导电薄膜的方法。在该方法中，惰性气体与反应气体混合，施加电能以在基本上接近大气压的压力下产生等离子体。该方法可用于沉积诸如二氧化硅，氮化硅，硅和金属膜的膜。

4. 发明授权

US06703326B2 High-pressure anneal process for integrated circuits 失效
标题翻译：集成电路的高压退火工艺
公开(公告)号：US06703326B2
公开(公告)日：2004-03-09
申请号：US10227334
申请日：2002-08-23
申请人： Richard H. Lane , Phillip G. Wald
发明人： Richard H. Lane , Phillip G. Wald
IPC分类号： H01L2126
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/324 , H01L29/513 , H01L29/518 , Y10S438/904 , Y10S438/908
摘要： This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized, sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.
摘要翻译：本发明体现了一种用于退火集成电路以修复制造引起的损伤的改进方法。集成电路在其中存在包含氢气的形成气体的加压密封室中进行退火。通过增加氢气到制造集成电路的材料的扩散速率，腔室的加压减小了最终退火步骤对总热暴露的贡献。理想地，除了氢气之外，形成气体还包含至少一种不与氢气反应的其它气体，例如氮气或氩气，从而降低爆炸危险。然而，集成电路可以仅包含保持在大于环境大气压的压力的氢气的环境中退火。

5. 发明授权

US06576572B2 Method of heating a substrate using a variable surface hot plate for improved bake uniformity 失效
标题翻译：使用可变表面加热板加热基材以提高烘烤均匀性的方法
公开(公告)号：US06576572B2
公开(公告)日：2003-06-10
申请号：US09990791
申请日：2001-11-16
申请人： Michael David Webster
发明人： Michael David Webster
IPC分类号： H01L2126
CPC分类号： H01L21/68707 , H01L21/67109 , H01L21/68728 , H01L21/68735 , H01L21/68778 , H01L21/68785
摘要： A system, method and apparatus are described for improving critical dimension uniformity in baked substrates. The system, method and apparatus provide for varying the distance between a substrate to be baked and the surface of a hot plate such that an approximately uniform temperature is obtained in the substrate during baking. In one embodiment, the substrate is positioned on a hot plate having a recess generally centered on its top side. The differences in distance between the edges of the substrates contacting the hot plate and the distance between the center region of the substrate and the bottom of the recess enable a generally uniform temperature to be obtained in the substrate.
摘要翻译：描述了一种系统，方法和装置，用于改善焙烧基材中的临界尺寸均匀性。该系统，方法和装置提供了改变要烘烤的基材和热板的表面之间的距离，使得在烘烤期间在基材中获得大致均匀的温度。在一个实施例中，基板定位在热板上，该热板具有通常以其顶侧为中心的凹槽。接触热板的基板的边缘与基板的中心区域与凹部的底部之间的距离的差异使得能够在基板中获得大致均匀的温度。

6. 发明授权

US06420282B1 Passivation of copper with ammonia-free silicon nitride and application to TFT/LCD 失效
标题翻译：用无氨氮化硅钝化铜并应用于TFT / LCD
公开(公告)号：US06420282B1
公开(公告)日：2002-07-16
申请号：US09658181
申请日：2000-09-08
申请人： John Batey , Peter M. Fryer , Jun Hyung Souk
发明人： John Batey , Peter M. Fryer , Jun Hyung Souk
IPC分类号： H01L2126
CPC分类号： H01L29/66765 , G02F2001/136295 , H01L21/28008 , H01L21/3185 , H01L27/124 , H01L29/4908 , H01L29/6675
摘要： A method for passivating copper, aluminum, or other refractory metal films using ammonia-free silicon nitride and structures produced by the method. A thin film transistor for use in a liquid crystal display and a method of constructing the same, wherein the transistor has a gate, a source and a drain, and a gate insulator between the gate and an active silicon layer. The improvement is a layer of the ammonia-free silicon nitride deposited between the copper,aluminum, or other refractory metal gate and the gate insulator. Further,. the gate is copper, aluminum, or another refractory metal and is deposited directly on the substrate. The layer of ammonia-free silicon nitride is also deposited on portions of the substrate adjacent the gate and the gate line extending therefrom. The layer is made in a plasma-enhanced chemical vapor deposition process wherein the gas mixture comprises one part silane to 135 parts nitrogen to 100 parts helium and 100 parts hydrogen. A structure, and a process for forming the structure, for providing stable and low-resistance electrical contact between copper,aluminum, or another refractory metal gate lines and a metallization layer of aluminum and/or molybdenum, includes using a conductive material, such as an indium tin oxide bridge. Prior to depositing the metallization layer, the copper,aluminum, or other refractory metal which extends over a portion of the conductive material, and a portion of the conductive material not covered by the copper,aluminum, or other refractory metal are passivated with a layer of the ammonia-free silicon nitride. The metallization layer is then connected to the conductive material through a via hole extending to that portion of the conductive material which is not covered by the copper, aluminum, or another refractory metal.
摘要翻译：一种使用无氨氮化硅钝化铜，铝或其它难熔金属膜的方法，以及通过该方法制造的结构。一种用于液晶显示器的薄膜晶体管及其构造方法，其中晶体管具有栅极，源极和漏极以及栅极与有源硅层之间的栅极绝缘体。改进之处在于沉积在铜，铝或其它难熔金属栅极与栅绝缘体之间的无氨氮化硅层。进一步，。门是铜，铝或另一难熔金属，并直接沉积在基底上。无氨氮化硅层也沉积在与栅极相邻的衬底的部分上以及从其延伸的栅极线上。该层由等离子体增强化学气相沉积工艺制成，其中气体混合物包含一部分硅烷至135份氮至100份氦和100份氢。铜，铝或另一难熔金属栅极线以及铝和/或钼的金属化层之间提供稳定且低电阻的电接触的结构和形成该结构的方法包括使用导电材料，例如氧化铟锡桥。在沉积金属化层之前，在导电材料的一部分上延伸的铜，铝或其它难熔金属以及未被铜，铝或其它难熔金属覆盖的导电材料的一部分被钝化，的无氨氮化硅。金属化层然后通过延伸到未被铜，铝或其他难熔金属覆盖的导电材料的那部分的通孔连接到导电材料。

7. 发明授权

US06235655B1 Semiconductor manufacturing system and semiconductor manufacturing method 失效
标题翻译：半导体制造系统和半导体制造方法
公开(公告)号：US06235655B1
公开(公告)日：2001-05-22
申请号：US09448590
申请日：1999-11-24
申请人： Tomohide Jozaki
发明人： Tomohide Jozaki
IPC分类号： H01L2126
CPC分类号： H01J37/32477 , H01J37/321
摘要： A problem in the manufacture of semiconductor wafers exists in that reaction product adhering to a quartz member is peeled off and falls on wafers, thus causing particles to contaminate the wafers. In system of introducing electro-magnetic waves from the outside via the quartz member, an inventive high-density plasma etching system for processing wafers by introducing electro-magnetic waves generated by a TCP electrode into a vacuum chamber via a quartz top board and by generating plasma by exciting gas within the chamber comprises a far infrared ray heater disposed above the quartz top board to heat the quartz top board by radiant heat of infrared rays generated from the far infrared ray heater, reducing the product adhering to the quartz member and thus the contaminating particles, thereby improving the yield of the wafers.
摘要翻译：制造半导体晶片的问题在于，粘附在石英部件上的反应产物被剥离并落在晶片上，从而导致颗粒污染晶片。在通过石英构件从外部引入电磁波的系统中，本发明的高密度等离子体蚀刻系统通过将由TCP电极产生的电磁波经由石英顶板引入真空室来处理晶片，并通过产生通过室内激发气体的等离子体包括设置在石英顶板上方的远红外线加热器，以通过从远红外线加热器产生的红外线的辐射热来加热石英顶板，从而减少粘附到石英构件上的产品，污染颗粒，从而提高晶片的产量。

8. 发明授权

US06171982B2 Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same 有权
标题翻译：用于对SOI衬底进行热处理的方法和装置及其制备方法
公开(公告)号：US06171982B2
公开(公告)日：2001-01-09
申请号：US09218416
申请日：1998-12-22
申请人： Nobuhiko Sato
发明人： Nobuhiko Sato
IPC分类号： H01L2126
CPC分类号： H01L21/3247 , H01L21/67115 , H01L21/76254 , H01L21/76256 , H01L21/76259
摘要： An SOI substrate having on the surface thereof a single crystal silicon film formed on an insulator is heat-treated in a hydrogen-containing reducing atmosphere in order to smooth the surface and reduce the boron concentration without damaging the film thickness uniformity in a single wafer and among different wafers. The method is characterized in that the single crystal silicon film is arranged opposite to a member of non-oxidized silicon for heat treatment.
摘要翻译：在其表面上形成有绝缘体的单晶硅膜的SOI衬底在含氢还原气氛中进行热处理，以平滑表面并降低硼浓度，而不损害单个晶片中的膜厚度均匀性，在不同的晶片之间。该方法的特征在于，将单晶硅膜与非氧化硅的构件相对地进行热处理。

9. 发明授权

US06825135B2 Elimination of dendrite formation during metal/chalcogenide glass deposition 有权
标题翻译：在金属/硫族化物玻璃沉积期间消除枝晶形成
公开(公告)号：US06825135B2
公开(公告)日：2004-11-30
申请号：US10164646
申请日：2002-06-06
申请人： Jiutao Li , Allen McTeer
发明人： Jiutao Li , Allen McTeer
IPC分类号： H01L2126
CPC分类号： H01L45/143 , C23C14/0688 , C23C14/541 , H01L45/085 , H01L45/141 , H01L45/1625 , H01L45/1641
摘要： A method of forming a programmable conductor memory cell array is disclosed wherein metal and chalcogenide glass are co-sputtered to fill an array of cell vias in a prepared substrate. The prepared substrate is heated above room temperature before the metal and chalcogenide glass film is deposited, and the heating is maintained throughout the deposition. The resulting metal/chalcogenide glass film has good homogeneity, a desired ratio of components, and has a regular surface.
摘要翻译：公开了一种形成可编程导体存储单元阵列的方法，其中金属和硫族化物玻璃被共溅射以填充制备的衬底中的一组电池通孔。在将金属和硫属元素化物玻璃膜沉积之前将制备的基材加热至室温以上，并且在整个沉积期间保持加热。所得的金属/硫族化物玻璃膜具有良好的均匀性，所需的组分比例，并且具有规则的表面。

10. 发明授权

US06818569B2 Method of fabricating annealed wafer 有权
标题翻译：制造退火晶圆的方法
公开(公告)号：US06818569B2
公开(公告)日：2004-11-16
申请号：US10323733
申请日：2002-12-20
申请人： Young-Hee Mun , Gun Kim , Sung-Ho Yoon
发明人： Young-Hee Mun , Gun Kim , Sung-Ho Yoon
IPC分类号： H01L2126
CPC分类号： H01L21/324 , H01L21/3221
摘要： A method of fabricating an annealed wafer of high quality by forming a defect-free active region of a device and controlling an irregular resistivity characteristic. The method includes a first annealing step of pre-heating a silicon wafer at a temperature of about 500° C. in a furnace in an ambience of a gas selected from the group consisting of Ar, N2 and an inert gas including Ar and N2; a second annealing step of changing the ambience of the gas into a 100% H2 gas ambience, increasing the temperature to 850° C.-1,150° C., and carrying out annealing for about an hour by maintaining the increased temperature; a third annealing step of changing the ambience of the gas into a 100% Ar gas ambience, increasing the temperature to about 1,200° C., and carrying out annealing for about an hour while the temperature of about 1,200° C. is maintained; and a temperature dropping step of decreasing the temperature in the furnace below about 500° C.
摘要翻译：通过形成器件的无缺陷有源区域并控制不规则电阻率特性来制造高质量的退火晶片的方法。该方法包括第一退火步骤，在选自Ar，N 2和包括Ar和N 2的惰性气体的气体的氛围下，在炉中在约500℃的温度下预热硅晶片; 将气体的气氛改变为100％H2气氛的第二退火步骤，将温度升高至850℃-1.150℃，并通过维持升高的温度进行约1小时的退火; 将气体的气氛改变为100％Ar气体环境的第三退火步骤，将温度升高至约1200℃，并且在保持约1200℃的温度下进行约1小时的退火; 以及降低炉内温度低于约500℃的降温步骤。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式