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1. 发明授权

US10256772B2 Shift control circuit and wireless device 有权
公开(公告)号：US10256772B2
公开(公告)日：2019-04-09
申请号：US15692673
申请日：2017-08-31
申请人： ICOM INCORPORATED
发明人： Yasuo Ueno
IPC分类号： H03D3/18 , H03C3/09 , H02J3/24 , H03C3/06 , H03G3/30 , H03J7/02 , H04B1/16 , H04N9/66 , H03G7/00 , H04B1/04
摘要： A signal input from a microphone is A-D converted by an A-D converter, is frequency differentiated by a pre-emphasis circuit, and is input to a shift control circuit. The shift control circuit includes a limiter circuit, a phase shifter, and a harmonic suppressor. The limiter circuit performs amplitude limitation so as to limit the amplitude of the input control target signal to be equal to or less than a first threshold. The phase shifter shifts, for the control target signal having the amplitude limited, a phase of a frequency component within the predetermined frequency range. The harmonic suppressor suppresses, for the control target signal phase-shifted by the phase shifter, a frequency component equal to or greater than a second threshold, and outputs an information signal that is the control target signal having the frequency component of equal to or greater than the second threshold suppressed. The modulator performs frequency modulation on a carrier wave in accordance with the information signal. The transmitter produces a transmission signal from the frequency-modulated carrier wave, and transmits the transmission signal via an antenna.

2. 发明申请

US20180091097A1 SHIFT CONTROL CIRCUIT AND WIRELESS DEVICE 审中-公开
公开(公告)号：US20180091097A1
公开(公告)日：2018-03-29
申请号：US15692673
申请日：2017-08-31
申请人： ICOM INCORPORATED
发明人： Yasuo Ueno
IPC分类号： H03C3/09 , H04B1/16 , H03D3/18 , H03C3/06 , H04N9/66 , H03G3/30 , H03J7/02 , H02J3/24
CPC分类号： H03C3/09 , H02J3/24 , H03C3/06 , H03D3/18 , H03G3/3063 , H03G7/002 , H03J7/02 , H04B1/0475 , H04B1/1661 , H04B2001/0425 , H04N9/66
摘要： A signal input from a microphone is A-D converted by an A-D converter, is frequency differentiated by a pre-emphasis circuit, and is input to a shift control circuit. The shift control circuit includes a limiter circuit, a phase shifter, and a harmonic suppressor. The limiter circuit performs amplitude limitation so as to limit the amplitude of the input control target signal to be equal to or less than a first threshold. The phase shifter shifts, for the control target signal having the amplitude limited, a phase of a frequency component within the predetermined frequency range. The harmonic suppressor suppresses, for the control target signal phase-shifted by the phase shifter, a frequency component equal to or greater than a second threshold, and outputs an information signal that is the control target signal having the frequency component of equal to or greater than the second threshold suppressed. The modulator performs frequency modulation on a carrier wave in accordance with the information signal. The transmitter produces a transmission signal from the frequency-modulated carrier wave, and transmits the transmission signal via an antenna.

3. 发明授权

US08705663B2 Receiver architecture and methods for demodulating binary phase shift keying signals 有权
标题翻译：用于解调二进制相移键控信号的接收机架构和方法
公开(公告)号：US08705663B2
公开(公告)日：2014-04-22
申请号：US14034426
申请日：2013-09-23
申请人： Innophase Inc.
发明人： Yang Xu
IPC分类号： H03D3/18 , H03D3/24
CPC分类号： H04L27/2272 , H04L27/2071 , H04L27/22
摘要： A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference.
摘要翻译：描述接收机。接收机包括第一注入锁定振荡器，其具有被配置为接收BPSK信号的第一输入和被配置为接收第一频率参考的第二输入。接收机还包括第二注入锁定振荡器，其具有被配置为接收BPSK信号的第三输入和被配置为接收第二频率参考的第四输入。此外，接收机包括与第一注入锁定振荡器的第二输入耦合的第一锁相环。第一锁相环被配置为产生第一频率参考。并且，第二锁相环与第二注入锁定振荡器的第四输入耦合。第二锁相环被配置为产生第二频率参考。

4. 发明授权

US08165247B1 Unfolded decision-directed loop, architectures, apparatuses and systems including the same, and methods, algorithms and software for reducing latency in decision-directed loops 有权
标题翻译：展开的决策环路，架构，设备和系统，包括相同的方法，算法和软件，用于减少决策环路中的延迟
公开(公告)号：US08165247B1
公开(公告)日：2012-04-24
申请号：US12337564
申请日：2008-12-17
申请人： Michael Madden , Zining Wu
发明人： Michael Madden , Zining Wu
IPC分类号： H03D3/18
CPC分类号： G11B20/10268
摘要： Unfolded adaptive/decision-directed loops and correction circuits therefor, architectures, apparatuses and systems including the same, and methods, algorithms and software for reducing latency in an adaptive and/or decision-directed loop. Disclosed embodiments advantageously reduce effects of loop latency, improve the accuracy of corrections in an adaptive loop, and minimize overhead and delays associated with such improvements.
摘要翻译：展开的自适应/决策导向环路及其校正电路，包括相同的架构，设备和系统以及用于减少自适应和/或决策导向环路中的延迟的方法，算法和软件。所公开的实施例有利地减少了环路延迟的影响，提高了自适应环路中校正的准确性，并最小化了与此类改进相关联的开销和延迟。

5. 发明授权

US08130874B2 By-pass arrangement of a low noise amplifier 有权
标题翻译：低噪声放大器的旁路布置
公开(公告)号：US08130874B2
公开(公告)日：2012-03-06
申请号：US11945363
申请日：2007-11-27
申请人： Mika Niemi
发明人： Mika Niemi
IPC分类号： H03D3/18 , H03F1/00
CPC分类号： H03F1/52 , H03F1/26 , H03F3/191 , H03F3/24 , H03F3/72 , H03F2200/294 , H03F2200/372 , H03F2203/7239 , H04B1/18
摘要： The invention relates to an arrangement for bypassing a low noise amplifier unit in the front stage of a radio receiver, especially intended for the base stations of mobile communication networks. The front stage includes, in succession, a divider (420), an amplifier unit (430) comprising two parallel, low noise amplifier branches, and a first combiner (450). The by-pass arrangement includes a second combiner (443), by which the halves (E11, E12) of the received signal are combined immediately after the divider before the amplification. A change-over switch (SW) is then used to select either the signal that has propagated through the amplifier unit and then combined (G·E1) or the signal (E1′) that has been directly combined as the output signal of the front stage. Due to the invention, the noise figure of the front stage is improved and the integration of its structure is facilitated.
摘要翻译：本发明涉及一种用于绕过无线电接收机的前级中的低噪声放大器单元的装置，特别是用于移动通信网络的基站。前级包括分压器（420），包括两个并联的低噪声放大器分支的放大器单元（430）和第一组合器（450）。旁路布置包括第二组合器（443），通过该第二组合器，接收信号的一半（E11，E12）在放大之前立即在分频器之后组合。然后使用转换开关（SW）来选择已经通过放大器单元传播的信号，然后组合（G·E1）或直接组合的信号（E1'）作为前端的输出信号阶段。由于本发明，前级的噪声系数得到改善，并且其结构的集成变得容易。

6. 发明授权

US07620126B2 Method and apparatus for detecting frequency lock in a system including a frequency synthesizer 失效
标题翻译：用于检测包括频率合成器的系统中的频率锁定的方法和装置
公开(公告)号：US07620126B2
公开(公告)日：2009-11-17
申请号：US11236658
申请日：2005-09-27
申请人： David William Boerstler , Matthew E. Fernsler , Eskinder Hailu , Jieming Qi , Mack Wayne Riley
发明人： David William Boerstler , Matthew E. Fernsler , Eskinder Hailu , Jieming Qi , Mack Wayne Riley
IPC分类号： H03D3/18
CPC分类号： H03L7/093 , H03L7/095
摘要： A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.
摘要翻译：公开了一种频率合成器锁定检测系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

7. 发明授权

US07535976B2 Apparatus and method for integration of tuner functions in a digital receiver 有权
标题翻译：在数字接收机中集成调谐器功能的装置和方法
公开(公告)号：US07535976B2
公开(公告)日：2009-05-19
申请号：US10902477
申请日：2004-07-30
申请人： Steven Jaffee , Donald McMullin , Ramon Gomez
发明人： Steven Jaffee , Donald McMullin , Ramon Gomez
IPC分类号： H03D3/18
CPC分类号： H04L27/38 , H03D3/009 , H03J1/005 , H04L2027/0016
摘要： A receiver to process a RF input signal having a plurality of channels includes a direct down conversion circuit, a demodulation circuit, and a local oscillator circuit. The direct down conversion circuit provides a downconverted signal based on the RF input signal and a local oscillator signal. The demodulation circuit receives the downconverted signal and provides a demodulated signal. The local oscillator circuit sets a frequency of the local oscillator signal based on a selected channel of the plurality of channels.
摘要翻译：用于处理具有多个通道的RF输入信号的接收器包括直接下变频电路，解调电路和本地振荡器电路。直接下变频电路基于RF输入信号和本地振荡器信号提供下变频信号。解调电路接收下变频信号并提供解调信号。本地振荡器电路基于多个信道的所选信道来设置本地振荡器信号的频率。

8. 发明申请

US20090122919A1 RECEIVER CIRCUIT, APPLICATION OF A FIRST AND A SECOND PROPORTIONAL ELEMENT OF A DIGITAL PLL STRUCTURE, AND METHOD FOR RECEIVING A FREQUENCY-SHIFT KEYED SIGNAL 有权
标题翻译：接收电路，数字PLL结构的第一和第二比例元件的应用，以及接收频移键控信号的方法
公开(公告)号：US20090122919A1
公开(公告)日：2009-05-14
申请号：US12269839
申请日：2008-11-12
申请人： Ulrich Grosskinsky
发明人： Ulrich Grosskinsky
IPC分类号： H03D3/18 , H04L27/14
CPC分类号： H04L27/1525
摘要： A receiver circuit, application of a first proportional element and a second proportional element of a digital PLL structure, and method for receiving a frequency-shift keyed signal are provided. A phase signal is calculated from an in-phase signal and a quadrature signal. A feedback signal is subtracted from the phase signal to form a difference signal. An output signal is determined from the difference signal by a nonlinear transfer function. The output signal is evaluated with an evaluation circuit. A first signal and a second signal are added to form a summation signal. The first signal is produced by multiplication of the output signal or the difference signal by a first proportionality factor. The second signal is produced by multiplication of the output signal or the first signal or the difference signal by a second proportionality factor, followed by integration, and the feedback signal is produced by integration of the summation signal.
摘要翻译：提供接收机电路，应用数字PLL结构的第一比例元件和第二比例元件以及接收频移键控信号的方法。相位信号由同相信号和正交信号计算。从相位信号中减去反馈信号，形成差分信号。通过非线性传递函数从差分信号确定输出信号。输出信号用评估电路进行评估。添加第一信号和第二信号以形成求和信号。第一信号是通过将输出信号或差分信号乘以第一比例因子而产生的。第二信号是通过将输出信号或第一信号或差分信号乘以第二比例因子产生的，随后是积分，并且通过求和信号的积分产生反馈信号。

9. 发明授权

US07443930B2 Complex digital phase locked loop for use in a demodulator and method of optimal coefficient selection 失效
标题翻译：用于解调器的复数数字锁相环和最佳系数选择方法
公开(公告)号：US07443930B2
公开(公告)日：2008-10-28
申请号：US10999531
申请日：2004-11-30
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H03D3/18 , H03D3/24
CPC分类号： H03D3/24 , H03D2200/0082
摘要： A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a controller, which multiplies the phase error by a gain factor selected to stabilize and optimize the phase locked loop and produces an output signal for use in extracting a frequency deviation present in the complex digital input signal. The output signal is also input to a numerically controlled oscillator that tracks the phase of the complex digital input signal based on the output signal and produces the complex digital feedback signal.
摘要翻译：用于数字解调器的复数数字锁相环包括相位检测器，用于产生指示复数数字输入信号和复数数字反馈信号之间的相位差的相位误差。将相位误差输入到控制器，该控制器将相位误差乘以所选择的增益因子，以稳定和优化锁相环，并产生用于提取复数字输入信号中存在的频率偏差的输出信号。输出信号也输入到数控振荡器，该振荡器基于输出信号跟踪复数数字输入信号的相位，并产生复数数字反馈信号。

10. 发明授权

US07424068B2 Method and system for coding/decoding signals and computer program product therefor 失效
标题翻译：用于编码/解码信号的方法和系统及其计算机程序产品
公开(公告)号：US07424068B2
公开(公告)日：2008-09-09
申请号：US10930715
申请日：2004-08-30
申请人： Giuseppe Visalli , Francesco Pappalardo , Giuseppe Avellone , Francesco Rimi , Agostino Galluzzo
发明人： Giuseppe Visalli , Francesco Pappalardo , Giuseppe Avellone , Francesco Rimi , Agostino Galluzzo
IPC分类号： H03D3/18
CPC分类号： H04L1/0059 , H03M13/256 , H04L1/0054 , H04L1/0068 , H04L25/067 , H04L27/2272 , H04L2027/0055 , H04L2027/0067
摘要： A method for decoding signals with encoded symbols over a symbol interval that modulate a carrier. The method includes phase locking the signal to be decoded to obtain a phase-locked signal. The value assumed by the phase-locked signal on at least one subinterval in each symbol interval is detected. The method continues with attributing to the decoded symbol corresponding to each symbol interval a value that is a function of the value detected the subinterval. The subinterval in question can be a single subinterval located at the end of the symbol interval. Alternatively, the value assumed by the phase-locked signal on a plurality of subintervals in each symbol interval is detected, and a respective majority value of said phase-locked signal within said plurality of subintervals is identified. A value determined on the basis of the majority value is attributed to the decoded symbol corresponding to each symbol interval.
摘要翻译：一种用于在调制载体的符号间隔上对具有编码符号的信号进行解码的方法。该方法包括对要解码的信号进行锁相以获得锁相信号。检测每个符号间隔中的至少一个子间隔上的锁相信号所假设的值。该方法继续归因于对应于每个符号间隔的解码符号，该值是检测到子间隔的值的函数。所涉及的子间隔可以是位于符号间隔结束处的单个子间隔。或者，检测每个符号间隔中的多个子间隔上的锁相信号所假设的值，并且识别所述多个子区间内的所述锁相信号的相应多数值。基于多数值确定的值归因于对应于每个符号间隔的解码符号。

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