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1. 发明授权

US06794897B2 High density antifuse based partitioned FPGA architecture 有权
标题翻译：高密度反熔丝分区FPGA架构
公开(公告)号：US06794897B2
公开(公告)日：2004-09-21
申请号：US10411627
申请日：2003-04-11
申请人： Reza Asayeh
发明人： Reza Asayeh
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： An antifuse based FPGA architecture is partitioned into repeatable blocks of logic modules to reduce the programming time of the array and to minimize parasitic capacitance and current leakage in the array. With repeatable blocks the size of the FPGA may be made larger with minimal changes to the architecture. Disposed along the edges of each repeatable block are bidirectional buffer banks for connecting to adjacent blocks and to an interconnect matrix that is connectable to blocks other than adjacent blocks. Disposed at regular intervals in the interconnect matrix are repeater buffers to limit the number of antifuses on a given track of the interconnect matrix, to minimize RC delay, and to avoid violating the Ipeak limit.
摘要翻译：基于反熔丝的FPGA架构被划分为可重复的逻辑模块，以减少阵列的编程时间并最小化阵列中的寄生电容和电流泄漏。对于可重复的块，可以通过对架构的最小改变来增加FPGA的尺寸。沿着每个可重复块的边缘布置的是用于连接到相邻块的双向缓冲器组和可连接到除了相邻块之外的块的互连矩阵。在互连矩阵中以规则间隔布置的是中继器缓冲器，以限制互连矩阵的给定轨道上的反熔丝数量，以最小化RC延迟，并避免违反Ipeak极限。

2. 发明授权

US06759870B2 Programmable logic array integrated circuits 有权
公开(公告)号：US06759870B2
公开(公告)日：2004-07-06
申请号：US10372373
申请日：2003-02-20
申请人： Richard G. Cliff , Bahram Ahanin , Craig Schilling Lytle , Francis B. Heile , Bruce B. Pedersen , Kerry Veenstra
发明人： Richard G. Cliff , Bahram Ahanin , Craig Schilling Lytle , Francis B. Heile , Bruce B. Pedersen , Kerry Veenstra
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , G01R31/318516 , G11C8/12 , H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/17792
摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

3. 发明授权

US06759869B1 Large crossbar switch implemented in FPGA 有权
标题翻译：在FPGA中实现大型交叉开关
公开(公告)号：US06759869B1
公开(公告)日：2004-07-06
申请号：US10164508
申请日：2002-06-05
申请人： Steven P. Young , Peter H. Alfke , Trevor J. Bauer , Colm P. Fewer
发明人： Steven P. Young , Peter H. Alfke , Trevor J. Bauer , Colm P. Fewer
IPC分类号： H03K19177
CPC分类号： H03K19/17748 , H03K19/17736 , H03K19/17752 , H03K19/17756 , H04Q3/0004 , H04Q3/521 , H04Q2213/13076
摘要： A method for using an FPGA to implement a crossbar switch is described. Rather than using signals routed through the general FPGA routing resources to control connectivity of the crossbar switch, the input signals only carry crossbar switch data, and the connectivity is controlled by FPGA configuration data. The crossbar switch is implemented in two parts: a template of basic and constant routing to carry input signals through the switch array in one dimension and output signals from the array in another dimension, and a connectivity part controlled by a connectivity table or algorithm to generate partial reconfiguration bitstreams that determine which of the input signals is to be connected to which of the output signals.
摘要翻译：描述了使用FPGA实现交叉开关的方法。不是使用通过通用FPGA路由资源路由的信号来控制交叉开关的连接，而是输入信号只带有交叉开关数据，连接由FPGA配置数据控制。交叉开关分两部分实现：基本和恒定路由的模板，通过一维的交换机阵列传送输入信号，并在另一维度上输出阵列的信号，以及由连接表或算法控制的连接部分，以产生部分重新配置比特流，其确定哪个输入信号要连接到哪个输出信号。

4. 发明授权

US06747482B2 Architecture and interconnect scheme for programmable logic circuits 失效
标题翻译：可编程逻辑电路的架构和互连方案
公开(公告)号：US06747482B2
公开(公告)日：2004-06-08
申请号：US10428724
申请日：2003-05-01
申请人： Benjamin S. Ting
发明人： Benjamin S. Ting
IPC分类号： H03K19177
CPC分类号： H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells that perform logical functions on input signals. A set of block connectors are used to provide connectability between cells and accessibility to a hierarchical routing network. Uniformly distributed layers of routing network lines re used to provide connections. Switching networks provide connectability between the routing network lines. Additional uniformly distributed layers of routing network lines. Programmable bi-directional passgates are used as switches to control which of the routing network lines are to be connected.
摘要翻译：用于现场可编程门阵列（FPGA）的架构和分布式分层互连方案。 FPGA由对输入信号执行逻辑功能的多个单元组成。一组块连接器用于提供小区之间的可连接性和对分层路由网络的可访问性。路由网络线路的均匀分布层被用来提供连接。交换网络提供路由网络线路之间的可连接性。额外均匀分布的路由网络线路层。可编程双向passgates用作开关，用于控制要连接的路由网络线路。

5. 发明授权

US06747480B1 Programmable logic devices with bidirect ional cascades 有权
标题翻译：具有直接级联的可编程逻辑器件
公开(公告)号：US06747480B1
公开(公告)日：2004-06-08
申请号：US10195209
申请日：2002-07-12
申请人： Sinan Kaptanoglu , Michael D. Hutton , James Schleicher
发明人： Sinan Kaptanoglu , Michael D. Hutton , James Schleicher
IPC分类号： H03K19177
CPC分类号： H03K19/17748 , H03K19/1737 , H03K19/17736
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. The regions of logic may include logic subregions that each have a look-up table. Interconnection resources (e.g., inter-region and intra-region interconnection conductors, signal buffers and drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections between the look-up tables. Programmable bidirectional cascade circuitry that is distinct from the interconnections may be used to make connections directly from the output of one look-up table to another without using the interconnection resources. The programmable cascade circuitry may be programmed so that multiple look-up tables are interconnected to form sequential cascade chains or cascade trees.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。逻辑区域可以包括各自具有查找表的逻辑子区域。在设备上提供互连资源（例如，区域间和区域内互连导体，信号缓冲器和驱动器，可编程连接器等），用于在查找表之间进行可编程互连。与互连不同的可编程双向级联电路可用于使连接从一个查找表的输出直接连接到另一个查找表，而不使用互连资源。可编程级联电路可以被编程，使得多个查找表互连以形成顺序级联链或级联树。

6. 发明授权

US06744278B1 Tileable field-programmable gate array architecture 有权
公开(公告)号：US06744278B1
公开(公告)日：2004-06-01
申请号：US10061951
申请日：2002-01-31
申请人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Naihui Liao
发明人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Naihui Liao
IPC分类号： H03K19177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.

7. 发明授权

US06731133B1 Routing structures for a tileable field-programmable gate array architecture 有权
标题翻译：用于瓦片现场可编程门阵列架构的路由结构
公开(公告)号：US06731133B1
公开(公告)日：2004-05-04
申请号：US10077190
申请日：2002-02-15
申请人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
发明人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
IPC分类号： H03K19177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： A field-programmable gate array (FPGA), comprising: a first FPGA tile, the first FPGA tile comprising a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile. The first FPGA tile also comprising a secondary routing structure independent of the regular routing structure, coupled to each of the IGs, configured to transfer signals from said first FPGA tile to at least one other FPGA tile. The disclosed apparatus also provides for a routing structure between IGs and RAM blocks. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understand that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：一种现场可编程门阵列（FPGA），包括：第一FPGA片，所述第一FPGA片包括多个功能组（FG），规则路由结构以及多个接口组（IG）。多个FG布置成行和列，其中每个FG被配置为接收常规输入信号，执行逻辑运算并产生规则的输出信号。常规路由结构耦合到FG并被配置成接收常规输出信号，在第一FPGA片内路由信号，并向FG提供常规输入信号。多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。每个IG耦合到常规路由结构并且被配置为将信号从常规路由结构传送到第一FPGA块的外部。第一FPGA片还包括独立于常规路由结构的辅路由结构，耦合到每个IG，被配置为将信号从所述第一FPGA片传送到至少另一个FPGA片。所公开的装置还提供了IG和RAM块之间的路由结构。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交的理由是，它不会用于解释或限制权利要求的范围或含义。

8. 发明授权

US06690193B1 One-time end-user-programmable fuse array circuit and method 有权
标题翻译：一次性最终用户可编程保险丝阵列电路及方法
公开(公告)号：US06690193B1
公开(公告)日：2004-02-10
申请号：US10227723
申请日：2002-08-26
申请人： Walter Heinzer , Azita Soroushian-Ashe , Pak W. Kung , Derek Bowers
发明人： Walter Heinzer , Azita Soroushian-Ashe , Pak W. Kung , Derek Bowers
IPC分类号： H03K19177
CPC分类号： G11C29/027 , G11C7/1045 , G11C17/14 , G11C17/18 , G11C29/028 , G11C29/08
摘要： A one-time end-user-programmable fuse array circuit suitable for providing a digital input to a programmable analog element such as a DAC. An end-user-specified digital bit pattern is conveyed to a programming circuit, which programs an array of data fuses in accordance with the specified pattern. A validation means indicates whether the states of the data fuses match the specified pattern. The programming circuit blows a “lock” fuse when the data fuses match the specified pattern, which prevents any additional data fuses from being programmed. The specified pattern and the states of the data fuses are multiplexed to a programmable analog element. Initially, the end-user can vary the pattern to achieve a desired result from the programmable element. When the desired result is achieved, the data fuses are blown, the resulting pattern is validated, and the lock fuse is blown—thereby providing a permanent trim signal.
摘要翻译：适用于向可编程模拟元件（如DAC）提供数字输入的一次性最终用户可编程保险丝阵列电路。最终用户指定的数字位模式被传送到编程电路，该编程电路根据指定的模式对数据熔丝阵列进行编程。验证装置指示数据保险丝的状态是否匹配指定的模式。当数据保险丝与指定的模式匹配时，编程电路会吹动“锁定”保险丝，从而防止任何额外的数据保险丝被编程。指定的模式和数据保险丝的状态被复用到可编程模拟元件。最初，最终用户可以改变模式以从可编程元件获得期望的结果。当达到期望的结果时，数据保险丝被熔断，所得到的模式被验证，并且锁保险丝被熔断，从而提供永久性的修整信号。

9. 发明授权

US06670825B1 Efficient arrangement of interconnection resources on programmable logic devices 有权
公开(公告)号：US06670825B1
公开(公告)日：2003-12-30
申请号：US10319320
申请日：2002-12-13
申请人： Christopher F. Lane , Giles V. Powell , Wayne Yeung , Chiakang Sung , Bruce B. Pedersen
发明人： Christopher F. Lane , Giles V. Powell , Wayne Yeung , Chiakang Sung , Bruce B. Pedersen
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： Interconnection block arrangements for selectively interconnecting logic on a programmable logic device is provided. Programmable logic connectors within the interconnection blocks may be programmed to route signals between the various conductors on the device and to route signals from various logic regions on the device to the various conductors. The interconnection blocks are arranged to optimize the use of metallization resources and to increase interconnectivity and logic density.

10. 发明授权

US06664807B1 Repeater for buffering a signal on a long data line of a programmable logic device 有权
标题翻译：用于在可编程逻辑器件的长数据线上缓冲信号的中继器
公开(公告)号：US06664807B1
公开(公告)日：2003-12-16
申请号：US10056724
申请日：2002-01-22
申请人： Patrick J. Crotty , Jinsong Oliver Huang
发明人： Patrick J. Crotty , Jinsong Oliver Huang
IPC分类号： H03K19177
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051 , G11C7/1078 , G11C7/1096 , H03K19/1776
摘要： A configuration memory array for a programmable logic device includes an array of configuration memory cells arranged in rows and columns. Initially, each of the configuration memory cells is reset to a reset state. Each row of configuration memory cells is coupled to a corresponding data line and data line driver. During configuration, each data line driver drives a configuration data value having a first state or a second state onto the corresponding data line. A configuration data value having the first state has a polarity that tends to flip the reset state of a configuration memory cell. A repeater cell is connected to an intermediate location of each data line. Each repeater cell improves the drive of configuration data values having the first state.
摘要翻译：用于可编程逻辑器件的配置存储器阵列包括以行和列布置的配置存储器单元的阵列。最初，每个配置存储单元被复位到复位状态。配置存储单元的每一行都耦合到相应的数据线和数据线驱动器。在配置期间，每个数据线驱动器将具有第一状态或第二状态的配置数据值驱动到相应的数据线上。具有第一状态的配置数据值具有趋向于翻转配置存储单元的复位状态的极性。中继器单元连接到每个数据线的中间位置。每个中继器单元改进具有第一状态的配置数据值的驱动。

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