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1. 发明申请

US20100244894A1 ENHANCED FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：增强现场可编程门阵列
公开(公告)号：US20100244894A1
公开(公告)日：2010-09-30
申请号：US12794279
申请日：2010-06-04
申请人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： H03K19/177
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

2. 发明授权

US06870396B2 Tileable field-programmable gate array architecture 有权
标题翻译：可拼接现场可编程门阵列架构
公开(公告)号：US06870396B2
公开(公告)日：2005-03-22
申请号：US10429004
申请日：2003-04-30
申请人： Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
发明人： Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17732
摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The routability of the regular routing structure is maximized by depositing switches according to designators. This novel designation method provides the same routability with approximately half the switches. Thus, further reduction in routing area is achieved. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.
摘要翻译：一种装置包括现场可编程门阵列（FPGA）。 FPGA包括第一FPGA片，并且第一FPGA片包括多个功能组（FG），规则路由结构以及多个接口组（IG）。多个FG布置成行和列，其中每个FG被配置为接收常规输入信号，执行逻辑运算并产生规则的输出信号。常规路由结构耦合到FG并被配置成接收常规输出信号，在第一FPGA片内路由信号，并向FG提供常规输入信号。通过根据指示符存放交换机来最大化常规路由结构的可路由性。这种新颖的指定方法与大约一半的开关提供相同的可路由性。因此，实现了路由区域的进一步减少。多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。每个IG耦合到常规路由结构并且被配置为将信号从常规路由结构传送到第一FPGA块的外部。

3. 发明授权

US06800884B1 Inter-tile buffer system for a field programmable gate array 有权
标题翻译：用于现场可编程门阵列的片间缓冲系统
公开(公告)号：US06800884B1
公开(公告)日：2004-10-05
申请号：US10334393
申请日：2002-12-30
申请人： Sheng Feng , Tong Liu , Jung-Cheun Lien
发明人： Sheng Feng , Tong Liu , Jung-Cheun Lien
IPC分类号： H01L2710
CPC分类号： H03K19/17736 , H01L27/118
摘要： The invention relates to an inter-tile buffering system for a field programmable gate array. The field programmable gate array is comprised of the following. A plurality of field programmable gate array tiles are arranged in an array of rows and columns. Each of said field programmable gate array tiles comprises a plurality of functional groups and a plurality of interface groups, and a primary routing structure. The primary routing structure is coupled to said functional groups and interface groups and is configured to receive primary output signals, route primary output signals within said at least one field programmable gate array tile, and provide primary input signals to said functional groups and interface groups. Each functional group is configured to receive primary input signals, perform a logic operation, and generate primary output signals. Each interface group is configured to transfer signals from said primary routing structure to outside of said at least one field programmable gate array tile, and includes a plurality of input multiplexers configured to select signals received from outside of said at least one field programmable gate array tile and provide signals to the primary routing structure inside said at least one field programmable gate array tile. Said primary routing structure comprises a horizontal bus and a vertical bus. A horizontal buffer is located between each column of field programmable gate array tiles and is coupled to the primary routing structure. A vertical buffer is located between each row of field programmable gate array tiles and is coupled to the primary routing structure.
摘要翻译：本发明涉及一种用于现场可编程门阵列的块间缓冲系统。现场可编程门阵列由以下组成。多个现场可编程门阵列瓦片被布置成行和列的阵列。每个所述现场可编程门阵列瓦片包括多个功能组和多个接口组以及主要路由结构。主路由结构耦合到所述功能组和接口组，并被配置为接收主要输出信号，在所述至少一个现场可编程门阵列瓦片内路由主输出信号，并向所述功能组和接口组提供初级输入信号。每个功能组被配置为接收主要输入信号，执行逻辑运算并产生主要输出信号。每个接口组被配置为将信号从所述主路由结构传送到所述至少一个现场可编程门阵列瓦片外部，并且包括多个输入多路复用器，其被配置为选择从所述至少一个现场可编程门阵列瓦片外部接收的信号并向所述至少一个现场可编程门阵列瓦片内的主路由结构提供信号。所述主路由结构包括水平总线和垂直总线。水平缓冲器位于每列现场可编程门阵列瓦片之间，并耦合到主路由结构。垂直缓冲器位于每行现场可编程门阵列瓦片之间，并耦合到主路由结构。

4. 发明授权

US06791353B1 Enhanced field programmable gate array 有权
标题翻译：增强型现场可编程门阵列
公开(公告)号：US06791353B1
公开(公告)日：2004-09-14
申请号：US09819084
申请日：2000-09-25
申请人： Samuel W. Beal , Sinan Kaptonoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptonoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： G06F738
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

5. 发明授权

US06744278B1 Tileable field-programmable gate array architecture 有权
公开(公告)号：US06744278B1
公开(公告)日：2004-06-01
申请号：US10061951
申请日：2002-01-31
申请人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Naihui Liao
发明人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Naihui Liao
IPC分类号： H03K19177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.

6. 发明授权

US06731133B1 Routing structures for a tileable field-programmable gate array architecture 有权
标题翻译：用于瓦片现场可编程门阵列架构的路由结构
公开(公告)号：US06731133B1
公开(公告)日：2004-05-04
申请号：US10077190
申请日：2002-02-15
申请人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
发明人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
IPC分类号： H03K19177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： A field-programmable gate array (FPGA), comprising: a first FPGA tile, the first FPGA tile comprising a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile. The first FPGA tile also comprising a secondary routing structure independent of the regular routing structure, coupled to each of the IGs, configured to transfer signals from said first FPGA tile to at least one other FPGA tile. The disclosed apparatus also provides for a routing structure between IGs and RAM blocks. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understand that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：一种现场可编程门阵列（FPGA），包括：第一FPGA片，所述第一FPGA片包括多个功能组（FG），规则路由结构以及多个接口组（IG）。多个FG布置成行和列，其中每个FG被配置为接收常规输入信号，执行逻辑运算并产生规则的输出信号。常规路由结构耦合到FG并被配置成接收常规输出信号，在第一FPGA片内路由信号，并向FG提供常规输入信号。多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。每个IG耦合到常规路由结构并且被配置为将信号从常规路由结构传送到第一FPGA块的外部。第一FPGA片还包括独立于常规路由结构的辅路由结构，耦合到每个IG，被配置为将信号从所述第一FPGA片传送到至少另一个FPGA片。所公开的装置还提供了IG和RAM块之间的路由结构。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交的理由是，它不会用于解释或限制权利要求的范围或含义。

7. 发明授权

US06446242B1 Method and apparatus for storing a validation number in a field-programmable gate array 有权
标题翻译：用于在现场可编程门阵列中存储验证号码的方法和装置
公开(公告)号：US06446242B1
公开(公告)日：2002-09-03
申请号：US09285563
申请日：1999-04-02
申请人： Jung-Cheun Lien , Sheng Feng , Chung-yuan Sun , Eddy Chieh Huang
发明人： Jung-Cheun Lien , Sheng Feng , Chung-yuan Sun , Eddy Chieh Huang
IPC分类号： G06F1750
CPC分类号： G06F21/121 , G06F17/5054
摘要： An apparatus including a field-programmable gate array (FPGA) where the FPGA includes a plurality of X signal lines, a plurality of Y signal lines, and a plurality of memory cells. A first set of the memory cells are used to implement programmable interconnections between the X and Y signal lines and logic functions such as are implemented by configurable functional blocks, and a second set of the memory cells are not used to implement programmable interconnections between the X and Y signal lines or logic functions. Configuration data that is used to implement a specific configuration of the programmable interconnections between the X and Y signal lines and the logic function is stored in the first set of memory cells, and at least a portion of a validation number is stored in at least some of the second set of memory cells. A method of configuring an FPGA includes storing configuration data used for configuring programmable interconnections among a plurality of X and Y signal lines and other logic functions in memory cells in the FPGA used for implementing the programmable interconnections and logic functions, and storing bits of data that form at least a portion of a validation number in memory cells in the FPGA that are not used for implementing the programmable interconnections or logic functions.
摘要翻译：一种包括现场可编程门阵列（FPGA）的装置，其中FPGA包括多条X信号线，多条Y信号线和多个存储单元。第一组存储器单元用于实现X和Y信号线之间的可编程互连以及诸如由可配置功能块实现的逻辑功能，并且第二组存储器单元不用于实现X之间的可编程互连和Y信号线或逻辑功能。用于实现X和Y信号线之间的可编程互连的特定配置和逻辑功能的配置数据被存储在第一组存储器单元中，并且验证号码的至少一部分被存储在至少一些的第二组存储单元。配置FPGA的方法包括存储用于在多个X和Y信号线之间配置可编程互连的配置数据以及用于实现可编程互连和逻辑功能的FPGA中的存储器单元中的其他逻辑功能，以及存储数据位形成FPGA中不用于实现可编程互连或逻辑功能的存储器单元中的验证号码的至少一部分。

8. 发明授权

US5698992A Programmable logic module and architecture for field programmable gate array device 失效
标题翻译：现场可编程门阵列器件的可编程逻辑模块和架构
公开(公告)号：US5698992A
公开(公告)日：1997-12-16
申请号：US746554
申请日：1996-11-13
申请人： Khaled A. El Ayat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
发明人： Khaled A. El Ayat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
IPC分类号： H03K19/177 , G01R31/28 , G01R31/3185 , H03K19/173
CPC分类号： G01R31/2884 , G01R31/318519 , H03K19/17704 , H03K19/17728
摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.
摘要翻译：用户可编程门阵列架构包括可包括一个或多个组合和/或顺序逻辑电路的逻辑功能模块阵列。包括多个水平和垂直通用互连通道的互连架构，每个通道互连通道包括多个互连导体，其中一些互连导体可能被分段，其被施加在阵列上。互连导体中的单个导体可通过用户可编程互连元件彼此连接并连接到逻辑功能模块的输入和输出端。包括本地互连通道的本地互连架构也被施加在阵列上。每个局部互连通道包括多个局部互连导体并且在相邻的逻辑功能模块对之间运行。

9. 发明授权

US5570041A Programmable logic module and architecture for field programmable gate array device 失效
公开(公告)号：US5570041A
公开(公告)日：1996-10-29
申请号：US504051
申请日：1995-06-28
申请人： Khaled A. El-Avat , Sinan Kaptanoglu , King W. Chan , William C. Plants , Jung-Cheun Lien
发明人： Khaled A. El-Avat , Sinan Kaptanoglu , King W. Chan , William C. Plants , Jung-Cheun Lien
IPC分类号： H01L21/82 , G01R31/28 , G01R31/3185 , H03K19/00 , H03K19/173 , H03K19/177
CPC分类号： G01R31/2884 , G01R31/318516 , G01R31/318519 , H03K19/177 , H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

10. 发明申请

US20070174803A1 Method for concurrent search and select of routing patterns for a routing system 审中-公开
标题翻译：路由系统的并发搜索和路由选择模式的方法
公开(公告)号：US20070174803A1
公开(公告)日：2007-07-26
申请号：US11651458
申请日：2007-01-10
申请人： Jung-Cheun Lien , Minchen Zhao
发明人： Jung-Cheun Lien , Minchen Zhao
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for concurrent search and select of routing patterns for a routing system is provided. The provided method introduces a metric for indicating the goodness of a routing pattern for guiding the selection of search engine at the route finding stage. Next, the method explores routes based on a plurality of feasible routing track segments that represent the longest continuous span of possible routes on a routing layer. Next, the preferred routing patterns can be selected. After that, the method goes to find one or more routing violations and then avoid the routing violations. Furthermore, the avoidance of the routing violation(s) can be implemented by reducing the length of the feasible routing track segment, or removing portion of a routed segment running in parallel and adjacent track(s) of the feasible routing track segment.
摘要翻译：提供了用于并行搜索和路由选择路由选择的方法。所提供的方法引入用于指示路由模式的优点的度量，用于在路线发现阶段指导搜索引擎的选择。接下来，该方法基于表示路由层上可能路由的最长连续跨度的多个可行路由轨道段来探索路由。接下来，可以选择优选的路由模式。之后，该方法会发现一个或多个路由违规，然后避免路由违规。此外，可以通过减少可行路由轨道段的长度或者去除在可行路由轨道段的并行和相邻轨道中运行的路由段的部分来实现路由违规的避免。

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