专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20200098305A1 PIXEL STRUCTURE 审中-公开
公开(公告)号：US20200098305A1
公开(公告)日：2020-03-26
申请号：US16527758
申请日：2019-07-31
申请人： AU Optronics Corporation
发明人： Chuang-Cheng YANG , Ming-Hsien LEE , Kai-Wei HONG , Yi-Cheng LIN , Chun-Feng LIN
IPC分类号： G09G3/32 , H03K17/00 , H03K25/02
摘要： The disclosure provides a light emitting diode including a light emitting diode (LED), a first transistor, a second transistor and capacitor. A cathode terminal of the LED is configured to receive a first power supply voltage. A first port of the capacitor coupled to the gate of the first transistor is configured to store a data signal in a first duration. A first port of the second transistor is configured to receive a second power supply voltage. A gate of the second transistor is configured to receive a PWM signal in a second duration. A second port of the second transistor is coupled to the second port of the first transistor. The second transistor is turned on for a conducting time in the second duration according to the PWM signal, and the first transistor provides, in the conducting time, a drive current to the LED according to the data signal.

2. 发明授权

US3989956A Charge transfer binary counter 失效
标题翻译：电荷转移二进制计数器
公开(公告)号：US3989956A
公开(公告)日：1976-11-02
申请号：US569273
申请日：1975-04-18
申请人： Robert Henry Walden
发明人： Robert Henry Walden
IPC分类号： H01L29/768 , H03K23/46 , H01L27/10 , H03K23/30 , H03K25/02
CPC分类号： H03K23/46 , H01L29/768
摘要： A two-phase charge transfer binary counter capable of counting the number of signal pulses in a particular time interval is described. The counter includes a charge storage medium in which is formed at least one charge storage "Q-cell" adapted to quantize each signal pulse into a charge packet. In tandem with the Q-cells are a plurality of one-bit shift registers each of which, except the last, comprises first and second charge storage cells connected in series. Adjacent cells of the same shift register are separated from one another by a threshold potential barrier of magnitude V.sub.T which permits only partial charge transfer thereacross. In contrast, adjacent cells of consecutive shift registers are separated from one another by a smaller transfer potential barrier of magnitude V.sub.B which permits virtually complete charge transfer thereacross. A feedback path is established between adjacent cells of the same shift register in order to clear residual charge from the first cell in response to charge transferred over its threshold barrier. At the end of the time interval, however, charge transfer ceases and the charge packets residing in the first cell of each shift register are the binary equivalent to the number of signal pulses in the time interval.
摘要翻译：描述了能够对特定时间间隔中的信号脉冲数进行计数的两相电荷转移二进制计数器。计数器包括电荷存储介质，其中形成有适于将每个信号脉冲量化为电荷分组的至少一个电荷存储“Q-单元”。与Q单元串联是多个一位移位寄存器，每个移位寄存器除了最后一个以外包括串联连接的第一和第二电荷存储单元。相同移位寄存器的相邻单元通过幅度VT的阈值电势势垒彼此分开，这仅允许跨越其中的部分电荷转移。相比之下，连续移位寄存器的相邻单元通过较小的量级VB的传输势垒彼此分离，这允许几乎完全的电荷转移。在相同移位寄存器的相邻单元之间建立反馈路径，以便响应于在其阈值屏障上传送的电荷来清除来自第一单元的剩余电荷。然而，在时间间隔结束时，电荷转移停止，并且驻留在每个移位寄存器的第一单元中的电荷分组是与时间间隔中的信号脉冲数的二进制值。

3. 发明授权

US3755793A Latent image memory with single-device cells of two types 失效
标题翻译：具有两种类型的单个设备细胞的最小图像存储器
公开(公告)号：US3755793A
公开(公告)日：1973-08-28
申请号：US3755793D
申请日：1972-04-13
申请人： IBM
发明人： HO I , MALEY G , HWA N YU
IPC分类号： G11C17/00 , G11C7/20 , G11C11/35 , G11C11/404 , G11C17/12 , H01L27/108 , G11C7/00 , G11C11/34 , H03K25/02
CPC分类号： G11C17/12 , G11C7/20 , G11C11/35 , G11C11/404 , H01L27/108
摘要： A latent image memory is selectively operable as either a readwrite memory or a read-only memory. The memory comprises an array of cells each preferably consisting of a single active device. A first set of the cells are each adapted to store either one of two binary digits. A second set of the cells are each responsive to a first condition for storing either one of two binary digits and responsive to a second condition for storing only a single predetermined binary digit. Means are provided for selecting either the first condition to render the array operable as a read-write memory, or the second condition to render the array operable as a read-only memory. Each of the cells of the first set preferably comprises a field-effect transistor connected to a capacitor, and each of the cells of the second set preferably comprises a charge-coupled device.
摘要翻译：潜像存储器可选择性地操作为读写存储器或只读存储器。存储器包括每个优选由单个有源器件组成的单元阵列。第一组单元适合于存储两个二进制数字之一。第二组单元各自响应用于存储两个二进制数字中的一个的第一条件，并响应于仅存储单个预定二进制数字的第二条件。提供了用于选择第一条件以使得阵列可操作为读写存储器的装置，或者用于使阵列可操作为只读存储器的第二条件。第一组的每个单元优选地包括连接到电容器的场效应晶体管，并且第二组的每个单元优选地包括电荷耦合器件。

4. 发明授权

US3578955A Totalizer for integrating the product of two variables with digital registration 失效
标题翻译：用于使用数字注册集成两个变量的产品的总计
公开(公告)号：US3578955A
公开(公告)日：1971-05-18
申请号：US3578955D
申请日：1968-03-18
申请人： RAMSEY ENG CO
发明人： KLOVEN GERALD P
IPC分类号： G01G23/37 , G06F7/68 , G06J1/00 , H03K25/02
CPC分类号： G06F7/68 , G01G23/37 , G06J1/00
摘要： A capacitor is charged with a DC current obtained from a voltage signal that is proportional to a first variable, such as the weight of material on a prescribed section of a conveyor belt. Each time that the accumulated charge on the capacitor reaches a specific level, the capacitor is automatically discharged to provide an output pulse. The repetition rate or frequency of these pulses is proportional to the signal voltage and hence the magnitude of the first variable. By causing these pulses, or a percentage of such pulses, to flow to a pulse counter, the count registered during the period of pulse flow will indicate the time integral of the first variable, and in the conveyor case the amount of conveyed material when the belt is moving at a constant speed. However, where the integral is influenced by another process variable, such as a variance in the conveyor belt speed, the count that is registered will not be an accurate indication of the total material discharged from the conveyor. Provision is made for modifying the number of pulses reaching the counter so that the total pulse count will reflect therein the variable belt speed. By way of an AC signal having a frequency proportional to the conveyor speed and circuitry controlled thereby, the current for charging the capacitor is alternately directed to the capacitor for a first period and then diverted from the capacitor for a second period. Means are employed for retaining the accumulated charge on the capacitor during each second period. In this way, pulses flow to the counter only during successive first periods and no pulses flow during successive second periods. By making the ratio of pulse flow time to total time, that is, the ratio of each first period to the sum of that first period and the following second period, proportional to the magnitude of the second variable, which is the belt speed in the illustrated situation, the counter registration then indicates the product of the two variables. In other words, there is produced a speed integral in which the counter registration denotes the quantity of material discharged from the conveyor even through both the rate of material and the belt speed vary. The capacitor is discharged many times each second. Pulsedivider circuitry accurately divides this high pulse rate down to a more usable range, thereby utilizing the above-mentioned percentage of pulses. A rate member is included and provision is made for providing a coarse zero and fine zero setting to indicate both zero rate on the meter and a zero counting rate on the counter for the condition of either (or both) the magnitude of the DC voltage or the frequency of the AC signal being zero. By means of a span adjustment a wide range in magnitudes of the DC input signal can be made to represent full scale on the rate meter.

5. 发明授权

US3544772A Electric bistable circuits 失效
标题翻译：电动电路
公开(公告)号：US3544772A
公开(公告)日：1970-12-01
申请号：US3544772D
申请日：1967-05-15
申请人： GEN ELECTRIC CO LTD
发明人： MORRIS RICHARD MICHAEL
IPC分类号： H03K3/00 , H03K3/28 , H03K23/74 , H03K25/02 , H03K23/03
CPC分类号： H03K23/74 , H03K3/00 , H03K3/28

6. 发明授权

US10748473B2 Pixel structure 有权
公开(公告)号：US10748473B2
公开(公告)日：2020-08-18
申请号：US16527758
申请日：2019-07-31
申请人： AU Optronics Corporation
发明人： Chuang-Cheng Yang , Ming-Hsien Lee , Kai-Wei Hong , Yi-Cheng Lin , Chun-Feng Lin
IPC分类号： G09G3/32 , H03K17/00 , H03K25/02 , H03K7/08 , H03K17/284 , G09G3/20
摘要： The disclosure provides a light emitting diode including a light emitting diode (LED), a first transistor, a second transistor and capacitor. A cathode terminal of the LED is configured to receive a first power supply voltage. A first port of the capacitor coupled to the gate of the first transistor is configured to store a data signal in a first duration. A first port of the second transistor is configured to receive a second power supply voltage. A gate of the second transistor is configured to receive a PWM signal in a second duration. A second port of the second transistor is coupled to the second port of the first transistor. The second transistor is turned on for a conducting time in the second duration according to the PWM signal, and the first transistor provides, in the conducting time, a drive current to the LED according to the data signal.

7. 发明授权

US3647940A Control system 失效
标题翻译：控制系统
公开(公告)号：US3647940A
公开(公告)日：1972-03-07
申请号：US3647940D
申请日：1970-12-01
申请人： LEOPOLD A HARWOOD
发明人： HARWOOD LEOPOLD A
IPC分类号： G11C27/02 , H03K25/02
CPC分类号： G11C27/024
摘要： A semiconductor device has a first and a second electrode interconnected with circuit means to form an electric circuit operable to control functions in an electric apparatus by changes in the conductivity of the first-second electrode current path. The device control electrode, which exhibits a high-input impedance, is coupled by a capacitor to a source cause potential. The capacitor is additionally connected to a source of control voltage adapted to change the charge state of the capacitor. A discharge path is provided for the capacitor and includes a switch to reset the voltage at the control electrode of the device to control the device first-second electrode current path conductivity such that the controlled function is adjusted to a predetermined condition. A plurality of circuits may be provided to control a plurality of functions in an apparatus. In such case, means are included for simultaneously actuating the switch means associated with each of the plurality of circuits so that the conductivity of the first-second electrode current path of the devices are simultaneously brought to reference levels which case the controlled functions to be simultaneously adjusted to predetermined conditions.
摘要翻译：半导体器件具有与电路装置互连的第一和第二电极，以形成可操作以通过第一 - 第二电极电流路径的电导率的变化来控制电气设备中的功能的电路。具有高输入阻抗的器件控制电极通过电容器耦合到源引起电位。电容器另外连接到适于改变电容器的充电状态的控制电压源。为电容器提供放电路径，并且包括用于复位器件的控制电极处的电压的开关，以控制器件的第一 - 第二电极电流通路电导率，使得受控功能被调整到预定条件。

8. 发明授权

US3646526A Fifo shift register memory with marker and data bit storage 失效
标题翻译：具有标记和数据位存储的FIFO移位寄存器存储器
公开(公告)号：US3646526A
公开(公告)日：1972-02-29
申请号：US3646526D
申请日：1970-03-17
申请人： US ARMY
发明人： FAGAN LLOYD D , HADDEN DAVID R JR , HARATZ DAVID , SARLO LORENZ M
IPC分类号： G06F5/06 , G11C19/18 , G11C19/00 , G11C11/24 , H03K25/02
CPC分类号： G11C19/184 , G06F5/06
摘要： A first-in, first-out (FIFO) memory having a plurality of memory cells, each for storing one data bit and one marker bit. The marker bit is provided for steering the data bits into successive memory cells when writing. Reading data is accomplished by shifting the data in succession out one end of the FIFO. Each memory cell consists only of MOS-transistors, which are connected so as to function as sample-and-hold devices and clocked inverter devices. One sample-and-hold transistor and one inverter each connected to the same clock will store a bit, either data or marker. Sample-and-hold transistors and inverters are coupled between the bit storage sections of common and adjacent memory cells so as to provide the proper logic for steering the data bits for shifting to adjacent cells the data and marker bits. The invention described herein may be manufactured, used, and licensed by or for the Government for governmental purposes without the payment to us of any royalty thereon.

9. 发明授权

US3593157A Voltage-controlled frequency divider 失效
标题翻译：电压控制分频器
公开(公告)号：US3593157A
公开(公告)日：1971-07-13
申请号：US3593157D
申请日：1969-05-29
申请人： BENDIX CORP
发明人： KOSAKOWSKI HENRY R
IPC分类号： H03B19/06 , H03K7/10 , H03K25/02
CPC分类号： H03K7/10 , H03B19/06
摘要： A frequency divider comprising a one-shot multivibrator operated by a fixed frequency pulse train applied to one of its inputs and controlled by a voltage signal to provide an output pulse train having a frequency corresponding to the voltage signal. The output pulse train is fed back to a second input of the multivibrator through a decay network to switch the multivibrator and the decay time t is controlled by the voltage signal. The frequency of the output pulse train is determined by the decay time t is controlled by the voltage signal. The frequency of the output pulse train is determined by the decay time t and varies from 1/t c.p.s. to the frequency of the input pulse train as determined by the magnitude of the voltage signal.

10. 发明授权

US3575612A Fet control system employing a storage capacitor and switching tube means 失效
标题翻译：使用存储电容器和切换管道的FET控制系统
公开(公告)号：US3575612A
公开(公告)日：1971-04-20
申请号：US3575612D
申请日：1968-05-31
申请人： RCA CORP
发明人： LUNN LAWRENCE M
IPC分类号： H03G1/02 , H03K25/02
CPC分类号： H03G1/02
摘要： A field effect transistor control unit having a storage capacitor associated with its gate electrode and employing a switching tube circuit arrangement to improve the ability of the unit to retain the charge on the capacitor.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式