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1. 发明授权

US06801062B2 Output circuit 有权
标题翻译：输出电路
公开(公告)号：US06801062B2
公开(公告)日：2004-10-05
申请号：US10345940
申请日：2003-01-17
申请人： Yasuyuki Okada
发明人： Yasuyuki Okada
IPC分类号： H03K300
CPC分类号： H03K19/00384 , H03D13/004
摘要： In a first and second logic circuit controlling a driver circuit of CMOS configuration having a plurality of output transistors connected in parallel, a delay fluctuation clock signal and a delay fluctuation data signal are generated by generating multi-phase data signals from multi-phase clock signals that each have a different phase difference with respect to a reference clock signal, and using a delay circuit having a variable delay time reflecting the change of the current driving capability of the output transistors in the driver circuit. Then, changes in the current driving capability of the output transistors are detected from a phase relation between the multi-phase data signals and the delay fluctuation data signal, and if it is detected that the current driving capability has decreased, then the number of output transistors that become conducting is increased, whereas if it is detected that the current driving capability has increased, then their number is decreased.
摘要翻译：在控制具有并联连接的多个输出晶体管的CMOS结构的驱动电路的第一和第二逻辑电路中，通过从多相时钟信号产生多相数据信号来产生延迟波动时钟信号和延迟波动数据信号每个相对于参考时钟信号具有不同的相位差，并且使用具有反映驱动器电路中的输出晶体管的电流驱动能力的变化的可变延迟时间的延迟电路。然后，根据多相数据信号和延迟波动数据信号之间的相位关系来检测输出晶体管的电流驱动能力的变化，并且如果检测到当前驱动能力已经减小，则输出数量成为导通的晶体管增加，而如果检测到电流驱动能力增加，则它们的数量减少。

2. 发明授权

US06768350B1 Microprocessor based solid state DC power controller 有权
标题翻译：基于微处理器的固态直流电源控制器
公开(公告)号：US06768350B1
公开(公告)日：2004-07-27
申请号：US10120091
申请日：2002-04-10
申请人： John A. Dickey
发明人： John A. Dickey
IPC分类号： H03K300
CPC分类号： H03K17/0822 , H03K17/063
摘要： A switching system includes a microcontroller that provides a powering signal to a solid state switch, such as a field effect transistor (FET). A powering signal from the microcontroller preferably is amplified using a charge pump to triple the magnitude of the signal from the microcontroller to provide a sufficient voltage to operate the gate of the FET. The microcontroller preferably provides the powering signal at least several cycles during a selected time period on a repeated, cyclical basis. During times when the controller is not providing the powering signal to operate the gate of the FET, the controller is free to perform other functions. Various other features, including over current monitoring are disclosed.
摘要翻译：开关系统包括向固态开关（例如场效应晶体管（FET））提供供电信号的微控制器。来自微控制器的供电信号优选地使用电荷泵进行放大，以使来自微控制器的信号的幅度加倍以提供足够的电压来操作FET的栅极。微控制器优选地在重复的循环基础上在选定的时间段期间提供至少几个周期的供电信号。在控制器没有提供供电信号来操作FET的栅极的时候，控制器可以自由执行其他功能。公开了包括过电流监测在内的各种其它特征。

3. 发明授权

US06734706B2 Circuit for driving a power device 有权
标题翻译：驱动电源设备的电路
公开(公告)号：US06734706B2
公开(公告)日：2004-05-11
申请号：US10252694
申请日：2002-09-24
申请人： Hiroshi Yoshida , Yoshikazu Tanaka
发明人： Hiroshi Yoshida , Yoshikazu Tanaka
IPC分类号： H03K300
CPC分类号： H03K17/162 , H03K17/063
摘要： A driving circuit includes a level shift circuit that shifts and outputs the level of the main signals consisting of the “ON” and “OFF” signals that respectively instruct ON and OFF of the power device, a transmitter circuit that latches the main signals to transmit to the power device, a mask signal circuit that generates a mask signal based on the main signals to prevent the transmission of the main signals when the logic of the “ON” and “OFF” signals becomes the same to cause false operation, a potential difference adding circuit that gives a potential difference &Dgr;V between a signal as the main signal input to the mask signal circuit and a signal as the main signal input to the transmitter circuit.
摘要翻译：驱动电路包括电平移位电路，其移位并输出由分别指示功率器件的导通和截止的“ON”和“OFF”信号组成的主信号的电平，锁存主信号以发送的发送器电路功率器件，掩模信号电路，其基于主信号产生掩蔽信号，以防止当“ON”和“OFF”信号的逻辑变为相同的主信号的传输以导致误操作时，电位差分加法电路，在作为输入到屏蔽信号电路的主信号的信号和作为输入到发送器电路的主信号的信号之间给出电位差ΔVa。

4. 发明授权

US06720801B2 RS-232 bus data tap apparatus 失效
标题翻译： RS-232总线数据分接设备
公开(公告)号：US06720801B2
公开(公告)日：2004-04-13
申请号：US09882987
申请日：2001-06-18
申请人： Christian Lauritz Houlberg
发明人： Christian Lauritz Houlberg
IPC分类号： H03K300
CPC分类号： G06F13/4286 , G06F11/349
摘要： A monitoring apparatus which allows the user to monitor transmit and receive data of half duplex communications taking place over a full duplex RS-232 bus and also monitor full duplex communications on the RS-232 bus. The monitoring apparatus includes six switching transistors which are turned on and off depending on input voltage levels appearing at the transmit and receive lines input to the monitoring apparatus from the RS-232 bus. Turning on and off the switching transistors enables a computer, lap top or other device connected to the monitoring apparatus to receive and process data communications on the RS-232 bus.
摘要翻译：一种监控装置，允许用户监视通过全双工RS-232总线进行的半双工通信的发送和接收数据，并监视RS-232总线上的全双工通信。监视装置包括根据从RS-232总线输入到监视装置的发送和接收线路上出现的输入电压电平而导通和截止的六个开关晶体管。打开和关闭开关晶体管可使计算机，笔记本或连接到监控设备的其他设备接收和处理RS-232总线上的数据通信。

5. 发明授权

US06707323B1 Semiconductor device, module having a plurality of semiconductor devices mounted thereon and system having a plurality of modules installed therein 有权
标题翻译：具有安装在其上的多个半导体器件的半导体器件模块和其中安装有多个模块的系统
公开(公告)号：US06707323B1
公开(公告)日：2004-03-16
申请号：US09666333
申请日：2000-09-21
申请人： Yasurou Matsuzaki , Masahiko Saitou
发明人： Yasurou Matsuzaki , Masahiko Saitou
IPC分类号： H03K300
CPC分类号： G11C29/021 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/12005 , G11C2029/5004 , H03K17/145
摘要： There is provided a semiconductor device having an output circuit for outputting a predetermined signal, and an output-level adjusting circuit for adjusting an output level of the output circuit in response to an adjustment start signal externally supplied and outputting an adjustment end signal upon completion of adjustment. A module in which a plurality of the semiconductor devices above are mounted. The module has an adjustment-start-signal terminal for receiving the adjustment start signal externally supplied and supplying the adjustment start signal to the semiconductor devices, and an adjustment-end-signal terminal for outputting a module adjustment end signal in response to adjustment end signals from the semiconductor devices. A plurality of such modules can be mounted in such a way that the adjustment-end-signal terminal of the (N−1)-th module is connected to the adjustment-start-signal terminal of the N-th module.
摘要翻译：提供了一种具有用于输出预定信号的输出电路的半导体器件，以及一个输出电平调整电路，用于响应外部提供的调整开始信号调整输出电路的输出电平，并在完成时输出调整结束信号调整。其中安装有上述多个半导体器件的模块。模块具有用于接收外部提供的调整开始信号并将调整开始信号提供给半导体器件的调整开始信号端子，以及用于响应于调整结束信号而输出模块调整结束信号的调整结束信号端子从半导体器件。可以以使第（N-1）个模块的调整结束信号端子连接到第N个模块的调整开始信号端子的方式安装多个这样的模块。

6. 发明授权

US06703874B2 Gate driver for MOS control semiconductor devices 失效
标题翻译：用于MOS控制半导体器件的栅极驱动器
公开(公告)号：US06703874B2
公开(公告)日：2004-03-09
申请号：US10436265
申请日：2003-05-13
申请人： Shuji Katoh , Shigeta Ueda , Hiromitsu Sakai , Takashi Ikimi , Tomomichi Ito
发明人： Shuji Katoh , Shigeta Ueda , Hiromitsu Sakai , Takashi Ikimi , Tomomichi Ito
IPC分类号： H03K300
CPC分类号： H02M1/32 , H03K17/0828 , H03K17/107
摘要： A gate driver is provided for controlling a gate voltage of each of a plurality of MOS control semiconductor devices, such as IGBTs or metal oxide MOS transistors, of a semiconductor power converter in which said MOS control semiconductors are connected in series with each other, the gate driver includes a power supply line having a higher potential than a gate potential on each of said MOS control semiconductor devices when in steady ON state, and an arrangement for supplying a current from the power source line to the gate of each of said MOS control semiconductors to increase the gate voltage of the MOS control semiconductor devices when a potential difference between said power supply line and an emitter of each of said MOS control semiconductors is constant and when a collector voltage of the MOS control semiconductor device exceeds a predetermined value under ON state of the MOS control semiconductor device.
摘要翻译：提供一种栅极驱动器，用于控制半导体功率转换器中的多个MOS控制半导体器件（例如IGBT或金属氧化物MOS晶体管）中的每一个的栅极电压，其中所述MOS控制半导体彼此串联连接，栅极驱动器包括在稳定导通状态时具有比每个所述MOS控制半导体器件上的栅极电位高的电位的电源线，以及用于将电流从电源线提供给每个所述MOS控制的栅极的装置半导体，当所述电源线和所述MOS控制半导体的每一个的发射极之间的电位差恒定时，以及当所述MOS控制半导体器件的集电极电压在ON时超过预定值时，增加所述MOS控制半导体器件的栅极电压 MOS控制半导体器件的状态。

7. 发明授权

US06693469B2 Buffer interface architecture 有权
标题翻译：缓冲区接口架构
公开(公告)号：US06693469B2
公开(公告)日：2004-02-17
申请号：US10128140
申请日：2002-04-23
申请人： Vladimir I. Prodanov
发明人： Vladimir I. Prodanov
IPC分类号： H03K300
CPC分类号： H03K19/00315 , H03K19/09429
摘要： An up to 3× breakdown voltage tristate capable integrated circuit CMOS buffer includes a level shifter circuit and a driver circuit. The driver stage includes a series connected n-channel and p-channel cascode stacks, each including at least three transistors. Dynamic gate biasing is provided for the third n-channel and p-channel cascode transistors to prevent voltage overstress of the cascode transistors. The level shifter circuit includes at least one pseudo N-MOS inverter including an input transistor, a protective cascode stack including at least one n-channel cascode transistor, and a load transistor. The level shifter provides at least one voltage shifted input signal to the driver.
摘要翻译：高达3x的击穿电压三态可集成电路CMOS缓冲器包括电平移位器电路和驱动电路。驱动器级包括串联连接的n沟道和p沟道共源共栅堆叠，每个包括至少三个晶体管。为第三n沟道和p沟道共源共栅晶体管提供动态栅极偏置，以防止共源共栅晶体管的电压过应力。电平移位器电路包括至少一个伪N-MOS反相器，其包括输入晶体管，包括至少一个n沟道共源共栅晶体管的保护共源共栅叠层和负载晶体管。电平移位器向驱动器提供至少一个电压偏移输入信号。

8. 发明授权

US06686779B2 Driver circuit for differentially outputting data from internal circuitry of an LSI to outside the LSI 失效
标题翻译：用于从LSI的内部电路将数据差分输出到LSI外部的驱动电路
公开(公告)号：US06686779B2
公开(公告)日：2004-02-03
申请号：US10227758
申请日：2002-08-27
申请人： Takefumi Yoshikawa
发明人： Takefumi Yoshikawa
IPC分类号： H03K300
CPC分类号： H04L25/028 , H03K19/00323 , H04L25/0272 , H04L25/0282
摘要： The driver circuit includes a constant current section, a first pad, a second pad, a first switching element, a second switching element, a first resistor, a second resistor, and a control section. The constant current section outputs a prescribed positive or negative current. The first switching element is connected between an output node of the constant current section and the first pad and turned ON/OFF in response to a first signal. The second switching element is connected between the output node of the constant current section and the second pad and turned ON/OFF in response to a second signal. The second signal is complementary to the first signal. The first resistor is connected between a first node receiving a first voltage and the first pad. The second resistor is connected between the first node and the second node. The control section controls a potential at the output node of the constant current section to a prescribed potential.
摘要翻译：驱动电路包括恒流部分，第一焊盘，第二焊盘，第一开关元件，第二开关元件，第一电阻器，第二电阻器和控制部件。恒定电流部分输出规定的正或负电流。第一开关元件连接在恒定电流部分的输出节点和第一焊盘之间，并响应于第一信号而导通/截止。第二开关元件连接在恒定电流部分的输出节点和第二焊盘之间，并响应于第二信号而导通/截止。第二信号与第一信号互补。第一电阻器连接在接收第一电压的第一节点和第一电池块之间。第二电阻器连接在第一节点和第二节点之间。控制部将恒定电流部的输出节点的电位控制为规定电位。

9. 发明授权

US06686778B2 High voltage tolerant differential input receiver 失效
标题翻译：高耐压差分输入接收器
公开(公告)号：US06686778B2
公开(公告)日：2004-02-03
申请号：US09935372
申请日：2001-08-22
申请人： Luke S. Theogarajan
发明人： Luke S. Theogarajan
IPC分类号： H03K300
CPC分类号： H03K17/102 , H03K19/00315
摘要： A computer system includes at least one high-voltage device and at least one low-voltage device. The low-voltage device has at least one differential input receiver, which reduces the risk of gate oxide stress by ensuring the voltage level on the low-voltage device gate(s) is at or below a predetermined value. The low-voltage device may be a memory controller and the high-voltage device may be a memory.
摘要翻译：计算机系统包括至少一个高压装置和至少一个低压装置。低压器件具有至少一个差分输入接收器，通过确保低压器件栅极上的电压等于或低于预定值来降低栅极氧化物应力的风险。低电压装置可以是存储器控制器，高电压装置可以是存储器。

10. 发明授权

US06677796B2 Method and apparatus for implementing precision time delays 失效
标题翻译：用于实现精确时间延迟的方法和装置
公开(公告)号：US06677796B2
公开(公告)日：2004-01-13
申请号：US09957646
申请日：2001-09-20
申请人： Vernon R. Brethour , Marcus H. Pendergrass , Ryan N. Confer
发明人： Vernon R. Brethour , Marcus H. Pendergrass , Ryan N. Confer
IPC分类号： H03K300
CPC分类号： H04B1/71635 , H03K5/13 , H03K5/135 , H03K5/159 , H03K2005/00156 , H04B1/71632
摘要： A system and method of implementing precision time delays that provides important and novel improvements over prior techniques of implementing time delays by utilizing a new strategy for selecting the values in the sine and cosine lookup tables. Sine and cosine values which result in non-uniform amplitudes enable increased overall accuracy with fewer bits communicated from the look-up tables to the analogue portion of the system. Further, herein is provided the addition of a variable amplitude threshold crossing capability following the combining of the sine and cosine signals. The time delay accuracy of the resulting phase and amplitude hybrid system can be improved either by increasing the number of bits in the sine/cosine phase management section or by increasing the number of bits in the amplitude section. There is provided herein an optimum strategy for choosing the number of bits used in the phase and amplitude sections for the best overall delay accuracy with the fewest overall control bits.
摘要翻译：实现精确时间延迟的系统和方法，通过利用用于选择正弦和余弦查找表中的值的新策略来实现对实现时间延迟的先前技术的重要和新颖的改进。导致非均匀幅度的正弦和余弦值使得从查找表传送到系统的模拟部分的较少比特数增加了总体精度。此外，这里提供了在正弦和余弦信号的组合之后添加可变幅度阈值交叉能力。可以通过增加正弦/余弦相位管理部分中的位数或通过增加幅度部分中的位数来提高所得到的相位和幅度混合系统的时间延迟精度。这里提供了用于选择在相位和幅度部分中使用的比特数的最佳策略，以获得具有最少总体控制比特的最佳总体延迟精度。

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