专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10873331B2 Clamp logic circuit 有权
公开(公告)号：US10873331B2
公开(公告)日：2020-12-22
申请号：US16102685
申请日：2018-08-13
申请人： RichWave Technology Corp.
发明人： Chih-Sheng Chen , Tien-Yun Peng
IPC分类号： H03K19/094 , H02H9/02 , H03K19/173 , H03H17/02 , H03K19/0175
CPC分类号： H03K19/09403 , H02H9/02 , H03H17/0248 , H03K19/0175 , H03K19/09429 , H03K19/1733 , H03K2217/0036 , H03K17/687 , G05F1/569 , H03F3/193 , H01L29/66
摘要： A clamp logic circuit has a logic circuit, a control terminal, a current clamp circuit and an output terminal. The logic circuit has at least a junction field-effect transistor (JFET). The control terminal receives an input signal. The current clamp circuit has a transistor and a resistor. A first end of the transistor is coupled to the control terminal, a second end of the transistor is coupled to a first end of the resistor, a control end of the transistor is coupled to a reference voltage, and a second end of the resistor is coupled to an input end of the logic circuit. The output terminal is coupled to an output end of the logic circuit.

2. 发明申请

US20180152188A1 System and Method of Driving a Switch Circuit 审中-公开
公开(公告)号：US20180152188A1
公开(公告)日：2018-05-31
申请号：US15590443
申请日：2017-05-09
申请人： Powerventure Semiconductor Limited
发明人： Der Ju Hung , Yuan Wen Hsiao , Chi-Chia Huang
IPC分类号： H03K19/0185 , H02M3/156 , G01S7/00 , H02J9/06 , H03K19/0948 , H03K19/094
CPC分类号： H02M3/156 , G01S7/00 , H02J9/06 , H03K17/163 , H03K17/284 , H03K19/01855 , H03K19/09429 , H03K19/0948 , H03K2017/515
摘要： A sequential driving method for driving a switch circuit of a power converter is presented. The method has the steps of driving a switch circuit which contains a power switch, defining a driving sequence; and applying sequentially an electrical parameter to the power switch, based on the driving sequence. Defining a driving sequence includes defining a plurality of different driving levels associated with the electrical parameter and defining a plurality of time windows within a switching time period. Each time window is associated with a driving level among the plurality of driving levels.

3. 发明授权

US09923555B2 Fine-grained power gating in FPGA interconnects 有权
公开(公告)号：US09923555B2
公开(公告)日：2018-03-20
申请号：US14777473
申请日：2014-03-14
申请人： The Regents of the University of California
发明人： Chengcheng Wang , Dejan Markovic
IPC分类号： H03K17/00 , H03K19/177 , H03K19/0185 , H03K19/00 , H03K19/173 , H03K19/094
CPC分类号： H03K17/005 , H03K19/0016 , H03K19/018528 , H03K19/09429 , H03K19/1737 , H03K19/17772
摘要： Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a PMOS transistor and an NMOS transistor, where at least one input to the inverter stage is provided to the gates of the PMOS and NMOS transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation.

4. 发明授权

US09595968B2 Cross point switch 有权
标题翻译：交叉开关
公开(公告)号：US09595968B2
公开(公告)日：2017-03-14
申请号：US14882262
申请日：2015-10-13
申请人： INTELLECTUAL VENTURES HOLDING 81 LLC
发明人： Robert P. Masleid , Scott Pitkethly
IPC分类号： H03K19/094 , H03K17/00
CPC分类号： H03K19/09429 , H03K17/002
摘要： A cross point switch, in accordance with one embodiment, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.
摘要翻译：根据一个实施例的交叉点开关包括耦合以形成多个多路复用器的多个三态中继器。多个多路复用器中的每组相应的三态中继器共享前端模块，使得与传统的交叉点开关相比，由于输入电容而导致的交叉点开关的延迟减小。

5. 发明申请

US20160269029A1 LOGICAL SIGNAL DRIVER WITH DYNAMIC OUTPUT IMPEDANCE AND METHOD THEREOF 审中-公开
标题翻译：具有动态输出阻抗的逻辑信号驱动器及其方法
公开(公告)号：US20160269029A1
公开(公告)日：2016-09-15
申请号：US14642887
申请日：2015-03-10
申请人： Realtek Semiconductor Corp.
发明人： Gerchih (Joseph) Chou , Chia-Liang (Leon) Lin
IPC分类号： H03K19/0185 , H03K19/094
CPC分类号： H03K19/018557 , H03K19/09429
摘要： In one embodiment, a method comprising receiving a logical signal; driving a source voltage at a first circuit node using a driver circuit in accordance with the logical signal; controlling an output impedance of the driver circuit using a finite state machine (FSM); transmitting the source voltage to a second circuit node via a transmission line; and terminating the second circuit node with a load circuit comprising a data detector.
摘要翻译：在一个实施例中，一种方法包括接收逻辑信号; 使用根据逻辑信号的驱动电路在第一电路节点处驱动源极电压; 使用有限状态机（FSM）控制驱动器电路的输出阻抗; 经由传输线将源电压传输到第二电路节点; 以及用包括数据检测器的负载电路终接第二电路节点。

6. 发明申请

US20160036428A1 Fine-Grained Power Gating in FPGA Interconnects 有权
标题翻译： FPGA互连中的细粒度电源门控
公开(公告)号：US20160036428A1
公开(公告)日：2016-02-04
申请号：US14777473
申请日：2014-03-14
申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
发明人： Chengcheng WANG , Dejan MARKOVIC
IPC分类号： H03K17/00 , H03K19/0185
CPC分类号： H03K17/005 , H03K19/0016 , H03K19/018528 , H03K19/09429 , H03K19/1737 , H03K19/17772
摘要： Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a PMOS transistor and an NMOS transistor, where at least one input to the inverter stage is provided to the gates of the PMOS and NMOS transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation.
摘要翻译：公开了根据本发明的实施例的用于逻辑和/或计算电路中的电源门控的系统和方法。在一个实施例中，用于细粒度功率选通的多路复用器包括第一电源电压和第二电源电压，多个输入，多个选择输入，配置成选择多个输入之一的选择电路，其中，所述多个输入是所述第一电源电压，并且所述选择输入中的一个是电源门控使能输入，包括PMOS晶体管和NMOS晶体管的输出反相器级，其中至少一个到所述反相器级的输入被提供给 PMOS和NMOS晶体管以及功率选通使能信号的选择将第一电源电压施加到PMOS晶体管的栅极，并将PMOS晶体管置于截止操作模式。

7. 发明申请

US20150091609A1 INTEGRATED CIRCUIT WITH SIGNAL ASSIST CIRCUITRY AND METHOD OF OPERATING THE CIRCUIT 有权
标题翻译：具有信号辅助电路的集成电路和操作电路的方法
公开(公告)号：US20150091609A1
公开(公告)日：2015-04-02
申请号：US14088570
申请日：2013-11-25
申请人： ARM LIMITED
发明人： Srinivasan SRINATH , Ambica ASHOK , Fakhruddin Ali BOHRA
IPC分类号： H03K19/017 , H03K19/094 , H03K19/00
CPC分类号： H03K19/01721 , G11C7/12 , G11C11/419 , H03K19/0013 , H03K19/09429 , H03K19/0963
摘要： An integrated circuit has signal assist circuitry for assisting with pulling a signal on the signal line towards the logical low or high signal level. The signal assist circuitry comprises first and second assist circuits. The first assist circuit couples the signal line to the logical high signal level following a pullup transition of the signal and provides a floating signal level following a pulldown transition, while the second assist circuit provides the floating signal level following the pullup transition and provides the logical low signal level following the pulldown transition. By providing complementary first and second assist circuits, each circuit can be optimized for the opposite transition to achieve improved performance or power consumption.
摘要翻译：集成电路具有信号辅助电路，用于帮助将信号线上的信号拉向逻辑低或高信号电平。信号辅助电路包括第一和第二辅助电路。第一辅助电路在信号的上拉转换之后将信号线耦合到逻辑高信号电平，并且在下拉转换之后提供浮动信号电平，而第二辅助电路在上拉跃迁之后提供浮动信号电平，并提供逻辑下拉转换后的低信号电平。通过提供互补的第一和第二辅助电路，每个电路可以针对相反的过渡进行优化，以实现改进的性能或功耗。

8. 发明申请

US20140340118A1 TRISTATE GATE 有权
标题翻译：三重门
公开(公告)号：US20140340118A1
公开(公告)日：2014-11-20
申请号：US14364923
申请日：2012-12-11
申请人： Soitec
发明人： Richard Ferrant
IPC分类号： H03K19/094 , H01L27/12 , H01L27/088
CPC分类号： H03K19/09429 , H01L27/0886 , H01L27/1203 , H03K19/094 , H03K19/0941
摘要： The present invention relates to a tristate gate (1000, 2000) comprising an output port (1400) and at least two transistors (1200, 1300; 2200, 2300), each having at least a first and a second gate, configured such that a high-impedance value (Z) on the output port is set by controlling the threshold voltage of at least one of the transistors.
摘要翻译：本发明涉及包括输出端口（1400）和至少两个晶体管（1200,1300,2200,2300）的三态门（1000,2000），每个至少具有第一和第二栅极，其被配置为使得通过控制至少一个晶体管的阈值电压来设定输出端口上的高阻抗值（Z）。

9. 发明申请

US20140219036A1 EQUALIZER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：均衡器和半导体存储器件包括它们
公开(公告)号：US20140219036A1
公开(公告)日：2014-08-07
申请号：US14165990
申请日：2014-01-28
申请人： Samsung Electronics Co., Ltd.
发明人： Dae-Hyun KIM , Seung-Jun BAE , Kyung-Soo HA
IPC分类号： G11C7/12 , H03K19/094 , G11C7/22
CPC分类号： G11C7/22 , G11C7/1048 , G11C7/1057 , H03K19/00361 , H03K19/09429
摘要： Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal.
摘要翻译：提供了一种均衡器和包括该均衡器的半导体存储器件。均衡器包括延迟电路和反相电路。延迟电路被配置为响应于选择信号输出延迟施加到输入/输出节点的输入信号的延迟信号和反相输入信号的反相信号之一。反相电路被配置为反转从延迟电路提供的信号并将反相信号输出到输入/输出节点。均衡器被配置为使得当延迟电路输出延迟信号时，均衡器用作放大输入信号并输出放大的输入信号的感应偏置电路，并且当延迟电路输出反相信号时，均衡器作为锁存器电路存储和输出输入信号。

10. 发明授权

US08476947B2 Duty cycle distortion correction circuitry 有权
公开(公告)号：US08476947B2
公开(公告)日：2013-07-02
申请号：US13295875
申请日：2011-11-14
申请人： John Henry Bui , Lay Hock Khoo , Khai Nguyen , Chiakang Sung , Ket Chiew Sia
发明人： John Henry Bui , Lay Hock Khoo , Khai Nguyen , Chiakang Sung , Ket Chiew Sia
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K19/018592 , H03K19/09429
摘要： Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式