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1. 发明授权

US10976409B2 Frequency-modulated continuous wave generator and frequency-modulated continuous wave radar system including the same 有权
公开(公告)号：US10976409B2
公开(公告)日：2021-04-13
申请号：US15818667
申请日：2017-11-20
申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
发明人： Ja Yol Lee , Bon Tae Koo
IPC分类号： G01S7/35 , H03F3/21 , H03F3/19 , H03L7/089 , H03L7/093 , H03L1/02 , H03L7/12 , G01S13/34 , H03B5/04 , H03B5/32
摘要： Provided is frequency-modulated continuous wave generator. The frequency-modulated continuous wave generator includes a ramp signal generator configured to generate an analog ramp signal, a reference signal generator configured to generate a reference signal based on the analog ramp signal, a phase locked loop configured to output a control voltage based on the reference signal, and a voltage-controlled oscillator configured to generate a frequency-modulated continuous wave based on the control voltage. The ramp signal generator is further configured to generate the analog ramp signal based on a feedback signal based on the frequency-modulated continuous wave.

2. 发明授权

US10340926B2 Fast settling sawtooth ramp generation in a phase-locked loop 有权
公开(公告)号：US10340926B2
公开(公告)日：2019-07-02
申请号：US15284190
申请日：2016-10-03
申请人： Analog Devices Global
发明人： Vamshi Krishna Chillara , Declan M. Dalton , Pablo Cruz Dato
IPC分类号： H03L7/00 , H03L7/093 , H03K4/90 , H03L7/099 , H03L7/10 , H03L7/107 , H03L7/12 , H03K3/80
摘要： Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.

3. 发明授权

US09083351B1 Phase lock loop with tracking filter for attenuating spurious signals of a swept local oscillator 有权
标题翻译：具有跟踪滤波器的锁相环，用于衰减扫频本地振荡器的杂散信号
公开(公告)号：US09083351B1
公开(公告)日：2015-07-14
申请号：US13794329
申请日：2013-03-11
申请人： Raytheon Company
发明人： Jack W. Lee , David M. Upton , Michael E. Yeomans , Marc S. Wald , James P. Dumais
IPC分类号： H03L7/00 , H03L7/02 , H03L7/12 , H01P1/20 , H03L7/093
CPC分类号： H03L7/12 , H01P1/20 , H03L7/0812 , H03L7/093
摘要： A high spectral purity swept local oscillator including a tracking filter. The output of a swept DDS oscillator may be improved by filtering it with a band-pass filter having an adjustable center frequency, which is adjusted in real time to track the instantaneous frequency of the DDS oscillator. The tracking may be accomplished by comparing, using a phase comparator, the phase at the output of the band-pass filter to the phase at its input, and feeding back to the frequency control input of the band-pass filter a signal corresponding to the phase difference measured by the phase comparator.
摘要翻译：包括跟踪滤波器的高频纯度扫频本地振荡器。扫描DDS振荡器的输出可以通过用具有可调节的中心频率的带通滤波器进行滤波来提高，该滤波器可以实时调整以跟踪DDS振荡器的瞬时频率。可以通过使用相位比较器将带通滤波器的输出端的相位与其输入端的相位进行比较，并将带通滤波器的频率控制输入反馈到与由相位比较器测量的相位差。

4. 发明授权

US08981855B2 Method and apparatus for drift compensation in PLL 有权
标题翻译： PLL中漂移补偿的方法和装置
公开(公告)号：US08981855B2
公开(公告)日：2015-03-17
申请号：US13854498
申请日：2013-04-01
申请人： Marvell World Trade Ltd.
发明人： Luca Romano , Randy Tsang
IPC分类号： H03L7/085 , H03L7/099 , H03L7/10 , H03L7/12
CPC分类号： H03L7/099 , H03J2200/10 , H03L7/085 , H03L7/103 , H03L7/12 , H03L2207/06
摘要： Aspects of the disclosure provide a phase-locked loop (PLL). The PLL includes a voltage-controlled oscillator (VCO), a detector module, and a ramp module. The VCO has a first capacitor unit and a second capacitor unit. The VCO is configured to generate an oscillating signal having a frequency based on a first capacitance of the first capacitor unit and a second capacitance of the second capacitor unit. The detector module is configured to generate a voltage signal as a function of the oscillating signal and a reference signal. The voltage signal is used to control the first capacitor unit to stabilize the frequency of the oscillating signal. The ramp module is configured to generate a ramp signal based on the voltage signal. The ramp signal is used to control the second capacitor unit to ramp the second capacitance from a first value to a second value.
摘要翻译：本公开的方面提供了锁相环（PLL）。 PLL包括压控振荡器（VCO），检测器模块和斜坡模块。 VCO具有第一电容器单元和第二电容器单元。 VCO被配置为产生具有基于第一电容器单元的第一电容的频率和第二电容器单元的第二电容的振荡信号。检测器模块被配置为产生作为振荡信号和参考信号的函数的电压信号。电压信号用于控制第一电容器单元以稳定振荡信号的频率。斜坡模块被配置为基于电压信号产生斜坡信号。斜坡信号用于控制第二电容器单元以将第二电容从第一值斜坡化为第二值。

5. 发明授权

US08884705B2 Frequency synthesis device with feedback loop 有权
标题翻译：具有反馈回路的频率合成装置
公开(公告)号：US08884705B2
公开(公告)日：2014-11-11
申请号：US13582808
申请日：2011-03-03
申请人： Emeric De Foucauld
发明人： Emeric De Foucauld
IPC分类号： H03L7/16 , H03L7/081 , H03L7/087 , H03L7/113 , H03L7/18 , H03L7/12
CPC分类号： H03L7/0812 , H03L7/087 , H03L7/113 , H03L7/12 , H03L7/16 , H03L7/18
摘要： A frequency synthesis device with a feedback loop includes: a phase-comparison control circuit; a frequency conversion unit voltage controlled by the control circuit; a feedback loop for supplying at least one signal issuing from the frequency conversion unit to the control circuit; at least one other control circuit for voltage control of the frequency conversion unit; and at least one other feedback loop for supplying at least one other signal issuing from the frequency conversion unit to the other control circuit.
摘要翻译：具有反馈回路的频率合成装置包括：相位比较控制电路; 由控制电路控制的变频单元电压; 反馈回路，用于将从变频单元发出的至少一个信号提供给控制电路; 至少一个用于所述变频单元的电压控制的控制电路; 以及至少一个其他反馈回路，用于将从频率转换单元发出的至少一个其它信号提供给另一个控制电路。

6. 发明授权

US5963608A Clock extractor for high speed, variable data rate communication system 失效
标题翻译：时钟提取器，用于高速，可变数据速率通信系统
公开(公告)号：US5963608A
公开(公告)日：1999-10-05
申请号：US882923
申请日：1997-06-26
申请人： Paul W. Casper , Marc E. Sawyer
发明人： Paul W. Casper , Marc E. Sawyer
IPC分类号： H03L7/095 , H03L7/12 , H03L7/197 , H04L7/033 , H04L25/03 , H04L25/49 , H03D3/24
CPC分类号： H03L7/12 , H04L25/03866 , H04L25/4904 , H04L7/033 , H03L7/095 , H03L7/197
摘要： To derive a clock embedded in a digital data stream, a variable data rate synchronizer includes a data rate estimator that derives an estimate of the data rate of data contained in the digital data signal, and a frequency estimator that derives an estimate of the frequency of the output of a voltage controlled oscillator. A phase lock loop includes a phase detector to which the digital data signal and the output of the voltage controlled oscillator are coupled and has an output coupled to a sweepable loop filter. The output of the loop filter is coupled to the voltage controlled oscillator. During an initital frequency acquisition mode, the sweep controller sequentially varies an analog voltage applied to the voltage controlled oscillator, until the estimate of the data rate effectively corresponds to the estimate of the frequency of the output of the voltage controlled oscillator. This terminates the frequency acquisition mode and initiates a phase acquisition mode, during which the sweep controller causes a sawtooth sweep of the loop filter, until the output of the loop filter corresponds to the actual frequency of said embedded clock signal, thereby locking the loop to the embedded clock.
摘要翻译：为了导出嵌入在数字数据流中的时钟，可变数据速率同步器包括导出数字数据信号中包含的数据的数据速率的估计的数据速率估计器，以及频率估计器，压控振荡器的输出。锁相环包括相位检测器，数字数据信号和压控振荡器的输出耦合到该相位检测器，并具有耦合到可扫描环路滤波器的输出。环路滤波器的输出耦合到压控振荡器。在初始频率获取模式期间，扫描控制器顺序地改变施加到压控振荡器的模拟电压，直到数据速率的估计对应于压控振荡器的输出频率的估计。这终止了频率获取模式，并且启动相位采集模式，在此期间，扫描控制器引起环路滤波器的锯齿波扫描，直到环路滤波器的输出对应于所述嵌入式时钟信号的实际频率，由此锁定环路嵌入式时钟。

7. 发明授权

US5838749A Method and apparatus for extracting an embedded clock from a digital data signal 失效
标题翻译：从数字数据信号中提取嵌入式时钟的方法和装置
公开(公告)号：US5838749A
公开(公告)日：1998-11-17
申请号：US462168
申请日：1995-06-05
申请人： Paul W. Casper , Jeffrey S. Grant , Marc E. Sawyer
发明人： Paul W. Casper , Jeffrey S. Grant , Marc E. Sawyer
IPC分类号： H03L7/095 , H03L7/12 , H03L7/197 , H04L7/033 , H04L25/03 , H04L25/49 , H04L7/00
CPC分类号： H04L7/033 , H03L7/12 , H04L25/03866 , H04L25/4904 , H03L7/095 , H03L7/197
摘要： A data and clock recovery arrangement, for a high speed fiber optic digital communication system in which a serial digital bit stream is pre-scramble encoded by interleaving complementary pairs of overhead bits between successive groups of data bits, and then scrambled and transmitted to a receive site, comprises a data rate independent variable bit rate synchronizer, a descrambler and a decoder. The data rate independent variable bit synchronizer processes the received scrambled and encoded digital bit stream to derive a variable data rate synchronization clock signal. The synchronizer is capable of accepting any data rate within the operational data clock signal range of the system, and automatically tunes itself to the data clock signal embedded in the received scrambled and encoded serial data stream, so as to output respective scrambled and encoded serial data and clock signals. The descrambler descrambles the scrambled and encoded serial digital bit stream using the variable data rate synchronization clock signal, and the decoder decodes the descrambled serial digital bit stream to extract groups of data bits exclusive of the complementary pairs of overhead bits and to derive an output clock signal having a frequency coincident with the data rate of the data bits.
摘要翻译：一种用于高速光纤数字通信系统的数据和时钟恢复装置，其中串行数字比特流通过在连续的数据比特组之间交织开销比特的互补对进行加密编码，然后被加扰并发送到接收包括数据速率独立的可变比特率同步器，解扰器和解码器。数据速率独立的可变位同步器处理接收的加密和编码的数字比特流以导出可变数据速率同步时钟信号。同步器能够接受系统的运行数据时钟信号范围内的任何数据速率，并自动调谐到嵌入在接收的经加扰和编码的串行数据流中的数据时钟信号，以输出相应的加扰和编码串行数据和时钟信号。解扰器使用可变数据速率同步时钟信号对加扰和编码的串行数字比特流进行解扰，并且解码器解码解扰的串行数字比特流以提取不同于开销比特的互补对的数据比特组，并且导出输出时钟信号具有与数据位的数据速率一致的频率。

8. 发明授权

US5699020A Phase latched differential charge pump circuit and method 失效
标题翻译：相锁相差动电荷泵电路及方法
公开(公告)号：US5699020A
公开(公告)日：1997-12-16
申请号：US668577
申请日：1996-06-20
申请人： David Edward Jefferson
发明人： David Edward Jefferson
IPC分类号： H03L7/087 , H03L7/089 , H03L7/095 , H03L7/107 , H03L7/12
CPC分类号： H03L7/107 , H03L7/0898 , H03L7/095 , H03L7/087 , Y10S331/02
摘要： A loop circuit such as a delay lock loop or a phase lock loop includes circuitry for changing the strength of the lock after lock has been achieved. Before lock is achieved, the strength of the charge pump circuitry that controls the charge in the low-pass filter in the loop may be relatively weak. After lock has been achieved, the strength of the charge pump circuit may be increased so that the circuit can maintain its locked condition in a noisy environment.
摘要翻译：诸如延迟锁定环或锁相环的回路电路包括用于在实现锁定之后改变锁的强度的电路。在实现锁定之前，控制环路中的低通滤波器中的电荷的电荷泵电路的强度可能相对较弱。在实现锁定之后，可以增加电荷泵电路的强度，使得电路可以在嘈杂的环境中保持其锁定状态。

9. 发明授权

US5521532A Digital synthesizer controlled microwave frequency signal source 失效
标题翻译：数字合成器控制微波频率信号源
公开(公告)号：US5521532A
公开(公告)日：1996-05-28
申请号：US318926
申请日：1994-10-06
申请人： Linley F. Gumm
发明人： Linley F. Gumm
IPC分类号： H03B23/00 , H03C3/09 , H03L7/091 , H03L7/18 , H03L7/20 , H03L7/12
CPC分类号： H03B23/00 , H03L7/20 , H03B2200/0092 , H03C3/0908 , H03L7/091 , H03L7/1806
摘要： A signal source provides an output signal which can sweep over a broad frequency range in a well-controlled manner. The signal source includes a voltage controlled oscillator (VCO) producing the output signal and a waveform synthesizer producing a reference signal. The VCO output signal is phase locked to the reference signal. To make the VCO signal continuously sweep over a broad frequency range, the reference signal sweeps repeatedly over a narrow frequency range. During each sweep of the reference signal, the VCO frequency tracks an integer harmonic of the reference signal frequency. The frequency and phase of the reference signal for each successive sweep are abruptly reset at the beginning of each sweep selected such that the VCO signal frequency locks to another integer harmonic of the reference signal frequency and does not change. Thus the VCO signal frequency sweeps continuously throughout the successive sweeps of the reference signal frequency but is unaffected by abrupt changes in reference signal frequency between successive reference signal frequency sweeps.
摘要翻译：信号源提供可以以良好控制的方式在宽频率范围上扫描的输出信号。信号源包括产生输出信号的压控振荡器（VCO）和产生参考信号的波形合成器。 VCO输出信号被锁相到参考信号。为了使VCO信号在宽频率范围内连续扫描，参考信号在窄频率范围内重复扫描。在参考信号的每次扫描期间，VCO频率跟踪参考信号频率的整数谐波。每个连续扫描的参考信号的频率和相位在选择的每个扫描的开始处突然复位，使得VCO信号频率锁定到参考信号频率的另一个整数谐波，并且不改变。因此，VCO信号频率在参考信号频率的连续扫描中连续扫描，但不受连续参考信号频率扫描之间的参考信号频率的突然变化的影响。

10. 发明授权

US5184092A Phase-locked loop frequency tracking device including a direct digital synthesizer 失效
标题翻译：锁相环频率跟踪装置包括直接数字合成器
公开(公告)号：US5184092A
公开(公告)日：1993-02-02
申请号：US899391
申请日：1992-06-16
申请人： Iradj Shahriary , Kevin M. McNab
发明人： Iradj Shahriary , Kevin M. McNab
IPC分类号： H03L7/099 , H03L7/10 , H03L7/12
CPC分类号： H03L7/0994 , H03L7/10 , H03L7/12
摘要： Disclosed is a single phase-locked loop (50, 350) providing tuning over a very large bandwidth for use in wide band carrier tracking and clock recovery systems. In a first embodiment, a DC signal is formed representative of a phase difference between an input signal changing with time and a return signal. The DC signal is applied to a narrow band voltage controlled oscillator (68) which converts the DC signal back to an AC signal. The AC signal is level shifted to form a clocking pulse for an accumulator (80) of a direct digital synthesizer (72). A digital command word is also applied to tyhe accumulator (80), such that the digital command word represents a coarse tuning of the input frequency. The clocking pulse from the narrow band VCO (68) supplies a fine tuning of the input frequency.
摘要翻译：公开了单个锁相环（50,350），其提供在非常大的带宽上的调谐以用于宽带载波跟踪和时钟恢复系统。在第一实施例中，形成DC信号，代表输入信号随时间变化和返回信号之间的相位差。 DC信号被施加到窄带压控振荡器（68），其将DC信号转换回AC信号。 AC信号被电平移位以形成用于直接数字合成器（72）的累加器（80）的时钟脉冲。数字命令字也被应用于累加器（80），使得数字命令字表示输入频率的粗调。来自窄带VCO（68）的时钟脉冲提供输入频率的微调。

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