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1. 发明授权

US11879963B2 Oscillator circuit, corresponding radar sensor, vehicle and method of operation 有权
公开(公告)号：US11879963B2
公开(公告)日：2024-01-23
申请号：US18108993
申请日：2023-02-13
申请人： STMicroelectronics S.r.l.
发明人： Alessandro Parisi , Andrea Cavarra , Alessandro Finocchiaro , Giuseppe Papotto , Giuseppe Palmisano
IPC分类号： G01S13/58 , G01S13/931 , H03B5/12 , H03L7/193 , H03L7/10 , G01S7/40 , H03L7/099
CPC分类号： G01S13/584 , G01S7/4056 , G01S13/931 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B5/1293 , H03L7/099 , H03L7/101 , H03L7/103 , H03L7/193
摘要： Disclosed herein is a tunable resonant circuit including an inductance directly electrically connected in series between first and second nodes, a variable capacitance directly electrically connected between the first and second nodes, and a set of switched capacitances coupled between the first and second nodes. The set of switched capacitances includes a plurality of capacitance units, each capacitance unit comprising a first capacitance for that capacitance unit directly electrically connected between the first node and a switch and a second capacitance for the capacitance unit directly electrically connected between the switch and the second node. Control circuitry is configured to receive an input control signal and connected to control the switches of the set of switched capacitances. A biasing circuit is directly electrically connected to the tunable resonance circuit at the first and second nodes.

2. 发明授权

US11646743B1 Digital phase-locked loop 有权
公开(公告)号：US11646743B1
公开(公告)日：2023-05-09
申请号：US17654073
申请日：2022-03-09
申请人： NXP USA, Inc.
发明人： Pawan Sabharwal , Anand Kumar Sinha , Krishna Thakur , Deependra Kumar Jain
IPC分类号： G04F10/00 , H03L7/095 , H03L7/10 , H03L7/099 , H03L7/107 , H03L7/093
CPC分类号： H03L7/103 , G04F10/005 , H03L7/093 , H03L7/095 , H03L7/0995 , H03L7/1075
摘要： A digital phase-locked loop (PLL) includes a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO). The DCO generates a PLL clock signal and various sampling clock signals that are mesochronous. The TDC samples a phase difference between a reference clock signal and a frequency-divided version of the PLL clock signal based on the sampling clock signals and various enable signals. The enable signals are generated based on a calibration of the digital PLL. Each enable signal is associated with a sampling clock signal and indicates whether the associated sampling clock signal is to be utilized for sampling the phase difference. Further, the TDC generates control data indicative of the sampled phase difference. The DCO generates the PLL clock signal and the sampling clock signals based on the control data until the digital PLL is in a phase-locked state.

3. 发明授权

US10056911B2 Continuous coarse-tuned phase locked loop 有权
公开(公告)号：US10056911B2
公开(公告)日：2018-08-21
申请号：US15385109
申请日：2016-12-20
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Gerd Rombach
IPC分类号： H03L7/06 , H03L7/099 , H03L7/10
CPC分类号： H03L7/099 , H03L7/103 , H03L2207/06
摘要： In some embodiments, a phase-locked loop (PLL) system comprises a phase-frequency detector (PFD) configured to compare a phase-frequency reference signal and a feedback signal, a charge pump (CP) electrically coupled to the PFD and configured to produce a first tuning signal based on an output of the PFD, multiple integrator cells electrically coupled to the CP and configured to output multiple second tuning signals based on a voltage of the first tuning signal relative to a voltage reference signal, and a voltage-controlled oscillator (VCO) electrically coupled to the CP and to the multiple integrator cells and configured to adjust a capacitance value of the VCO based on the multiple second tuning signals. The capacitance value and the first tuning signal affect a frequency of the feedback signal.

4. 发明授权

US09094026B2 Digital phase-locked loop device with automatic frequency range selection 有权
标题翻译：具有自动频率范围选择的数字锁相环装置
公开(公告)号：US09094026B2
公开(公告)日：2015-07-28
申请号：US14273721
申请日：2014-05-09
申请人： Asahi Kasei Microdevices Corporation
发明人： David Canard , Sebastien Charpentier , Matthieu Lecuyer
IPC分类号： H03L7/085 , H03L7/089 , H03L7/099 , H03L7/093 , H03L7/10 , H03L7/197
CPC分类号： H03L7/0992 , H03L7/093 , H03L7/099 , H03L7/103 , H03L7/1976 , H03L2207/06
摘要： A digital phase-locked loop (PLL) device includes a digital loop filter which is provided with both a VCO-loop output and a DCO-loop output. The VCO-loop output is connected to an analog input of a multiband voltage-controlled oscillator (VCO) module for allowing usual operation of the PLL with a direct voltage acting as feedback parameter. The DCO-loop output is connected to a digital control input of the multiband VCO module for allowing automatic frequency range selection. A code value which is produced by the digital loop filter acts as feedback parameter during the frequency range selection. Rapid and precise range selection can thus be performed.
摘要翻译：数字锁相环（PLL）器件包括一个数字环路滤波器，同时具有VCO环路输出和DCO环路输出。 VCO环路输出连接到多频段压控振荡器（VCO）模块的模拟输入，用于允许PLL作为反馈参数的直流电压的常规操作。 DCO环路输出连接到多频段VCO模块的数字控制输入，用于允许自动频率范围选择。由数字环路滤波器产生的码值在频率范围选择期间作为反馈参数。因此可以进行快速精确的范围选择。

5. 发明授权

US09048850B2 Frequency synthesizer apparatus and methods for improving capacitor code search accuracy using LSB modulation 有权
标题翻译：使用LSB调制改善电容码搜索精度的频率合成器装置和方法
公开(公告)号：US09048850B2
公开(公告)日：2015-06-02
申请号：US13797356
申请日：2013-03-12
申请人： QUALCOMM Incorporated
发明人： Abbas Komijani , Emmanouil Terrovitis , Justin A. Hwang
IPC分类号： H03L7/10 , H03L7/087 , H03J5/24 , H03L7/113 , H03L7/181
CPC分类号： H03L7/103 , H03J5/244 , H03J2200/10 , H03L7/087 , H03L7/10 , H03L7/113 , H03L7/181 , H03L2207/06
摘要： A frequency synthesizer is disclosed that includes an oscillator having an output to deliver a signal of a controllable frequency. The oscillator includes a capacitor bank responsive to an N-bit control signal to exhibit a capacitance. The oscillator output frequency is based on the capacitance. Control logic generates the N-bit control signal and determines each bit of the N-bit control signal through a binary search step and a modulation of a least-significant-bit (LSB) of the N-bit control signal. The LSB modulation, combined with the binary search for each bit, results in a higher accuracy frequency estimation.
摘要翻译：公开了一种频率合成器，其包括具有输出以输送可控频率的信号的振荡器。振荡器包括响应于N位控制信号以显示电容的电容器组。振荡器输出频率基于电容。控制逻辑产生N位控制信号，并且通过二进制搜索步骤和N位控制信号的最低有效位（LSB）的调制来确定N位控制信号的每个位。 LSB调制与每个比特的二进制搜索相结合，导致更高的频率估计精度。

6. 发明授权

US09008253B2 Control method for selecting frequency band and related clock data recovery device 有权
标题翻译：选择频带和相关时钟数据恢复装置的控制方法
公开(公告)号：US09008253B2
公开(公告)日：2015-04-14
申请号：US13775119
申请日：2013-02-23
申请人： NOVATEK Microelectronics Corp.
发明人： Tzu-Chien Tzeng , Hung-Yi Cheng
IPC分类号： H03D3/24 , H04L7/033 , H03L7/08 , H03L7/10 , H03L7/107
CPC分类号： H04L7/0331 , H03L7/0807 , H03L7/103 , H03L7/1072 , H04L7/033
摘要： A control method utilized in a clock data recovery device supporting a plurality of frequency bands, for controlling the clock data recovery device to select an operating frequency band from the plurality of frequency bands and to generate a recovery clock for generating retimed data, includes receiving a serial data stream with a data frequency; making each frequency band of the plurality of frequency bands correspond to a plurality of frequency band groups, wherein each frequency band group includes at least one frequency band and corresponds to different frequency ranges; selecting a frequency band group from the plurality of frequency band groups as a coarse-tuned frequency band group according to the data frequency and a locking voltage range; and selecting a frequency band from the plurality of frequency bands according to the data frequency, the locking voltage range and the coarse-tuned frequency band group for generating the recovery clock.
摘要翻译：一种在支持多个频带的时钟数据恢复装置中使用的控制方法，用于控制时钟数据恢复装置从多个频带中选择工作频带并产生用于产生重新定时数据的恢复时钟，包括：具有数据频率的串行数据流; 使多个频带的每个频带对应于多个频带组，其中每个频带组包括至少一个频带并对应于不同的频率范围; 根据数据频率和锁定电压范围，从多个频带组中选择频带组作为粗调谐频带组; 以及根据数据频率，锁定电压范围和用于产生恢复时钟的粗调谐频带组从多个频带中选择频带。

7. 发明申请

US20140347137A1 ADJUSTING TUNING SEGMENTS IN A DIGITALLY-CONTROLLED OSCILLATOR 有权
标题翻译：调整数字控制振荡器中的调谐部分
公开(公告)号：US20140347137A1
公开(公告)日：2014-11-27
申请号：US13901481
申请日：2013-05-23
申请人： Intel IP Corporation
发明人： Claudio REY , David HARNISHFEGER , Darin NGUYEN
IPC分类号： H03L7/16
CPC分类号： H03L7/099 , H03B5/124 , H03L7/103 , H03L7/18 , H03L2207/06
摘要： A circuit may include a digitally-controlled oscillator including a coarse frequency-tuning array with a multiple selectable coarse frequency-tuning segments. Each of the coarse frequency-tuning segments may have a coarse segment frequency step size. The digitally-controlled oscillator may also include a fine frequency-tuning array with multiple selectable fine frequency-tuning segments. The fine frequency-tuning array may have a fine array frequency step size that is at least twice the coarse segment frequency step size. The digitally-controlled oscillator may be configured to generate an output signal with a frequency based on the coarse frequency-tuning array and the fine frequency-tuning array.
摘要翻译：电路可以包括数字控制振荡器，其包括具有多个可选粗略频率调谐段的粗调频调谐阵列。每个粗调频段可以具有粗段频率步长。数字控制振荡器还可以包括具有多个可选精细频率调谐段的精细频率调谐阵列。精细的频率调谐阵列可以具有至少是粗略段频率步长的两倍的精细阵列频率步长。数字控制振荡器可以被配置为基于粗调频调谐阵列和精细频率调谐阵列产生具有频率的输出信号。

8. 发明申请

US20140320183A1 PLL FREQUENCY SYNTHESIZER WITH MULTI-CURVE VCO IMPLEMENTING CLOSED LOOP CURVE SEARCHING USING CHARGE PUMP CURRENT MODULATION 有权
标题翻译： PLL频率合成器，具有多曲线VCO使用充电泵电流调制实现闭合环路曲线搜索
公开(公告)号：US20140320183A1
公开(公告)日：2014-10-30
申请号：US13874222
申请日：2013-04-30
申请人： Micrel, Inc.
发明人： Juinn-Yan Chen , Wei-Kang Cheng
IPC分类号： H03L7/085
CPC分类号： H03L7/103 , H03L5/00 , H03L7/099 , H03L7/1072 , H03L7/1976 , H03L2207/06
摘要： A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a phase and frequency detector driving a charge pump and a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit increases the charge pump current above a nominal current value during the closed loop curve search operation and set the charge pump current to the nominal current value after an operating curve is selected.
摘要翻译：使用具有一组操作曲线的多曲线压控振荡器（VCO）的锁相环电路，每个操作曲线对应于在控制电压范围上的不同频率范围。锁相环电路包括驱动电荷泵的相位和频率检测器和配置成使用闭环曲线搜索操作产生曲线选择信号的数字控制电路，以选择多曲线VCO中的一个操作曲线，所选择的操作曲线被VCO使用以产生输出频率等于或接近锁相环的目标频率的输出信号。在一个实施例中，在闭环曲线搜索操作期间，数字控制电路将电荷泵电流增加到额定电流值以上，并且在选择操作曲线之后将电荷泵电流设置为标称电流值。

9. 发明授权

US08421542B2 Method and apparatus for drift compensation in PLL 有权
公开(公告)号：US08421542B2
公开(公告)日：2013-04-16
申请号：US13104404
申请日：2011-05-10
申请人： Luca Romano , Randy Tsang
发明人： Luca Romano , Randy Tsang
IPC分类号： H03L7/08
CPC分类号： H03L7/099 , H03J2200/10 , H03L7/085 , H03L7/103 , H03L7/12 , H03L2207/06
摘要： Aspects of the disclosure provide a phase-locked loop (PLL). The PLL includes a voltage-controlled oscillator (VCO), a detector module, and a ramp module. The VCO has a first capacitor unit and a second capacitor unit. The VCO is configured to generate an oscillating signal having a frequency based on a first capacitance of the first capacitor unit and a second capacitance of the second capacitor unit. The detector module is configured to generate a voltage signal as a function of the oscillating signal and a reference signal. The voltage signal is used to control the first capacitor unit to stabilize the frequency of the oscillating signal. The ramp module is configured to generate a ramp signal based on the voltage signal. The ramp signal is used to control the second capacitor unit to ramp the second capacitance from a first value to a second value.

10. 发明申请

US20130009681A1 ADPLL CIRCUIT, SEMICONDUCTOR DEVICE, AND PORTABLE INFORMATION DEVICE 有权
标题翻译：辅助电路，半导体器件和便携式信息器件
公开(公告)号：US20130009681A1
公开(公告)日：2013-01-10
申请号：US13616449
申请日：2012-09-14
申请人： Ryo ENDO , Jiro SHIMBO , Tomomitsu KITAMURA
发明人： Ryo ENDO , Jiro SHIMBO , Tomomitsu KITAMURA
IPC分类号： H03L7/08
CPC分类号： H03L7/113 , H03L7/099 , H03L7/103 , H03L2207/06 , H03L2207/50
摘要： The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.
摘要翻译：本发明提供了在ADPLL环境或靠近ADPLL环境的环境下的ABS精度改进手段，实现了ABS的加工时间缩短。在ABS电路中的数字频率比较器中，准备用于存储从DPFD输出的DPE信号中的初始相位差的DFF。在ABS操作开始之后，从DPFD输出的DPE信号被记录为将DPFD的内部电路中的初始相位差表示为DFF的信号。之后，数字频率比较器通过使用从输入DPE信号中减去记录在DFF中的初始相位误差获得的信号来执行ABS，从而实现高速和稳定的ABS操作。

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