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1. 发明申请

US20180167234A1 NON-TRANSITORY COMPUTER-READABLE MEDIUM STORING INSTRUCTIONS 审中-公开
公开(公告)号：US20180167234A1
公开(公告)日：2018-06-14
申请号：US15892205
申请日：2018-02-08
申请人： BROTHER KOGYO KABUSHIKI KAISHA
发明人： Norihiko ASAI
IPC分类号： H04L13/08 , H04W4/80 , H04M11/00
CPC分类号： H04L13/08 , H04L67/34 , H04M11/007 , H04W4/023 , H04W4/80 , H04W40/22 , H04W60/02 , H04W88/02 , H04W88/06
摘要： A non-transitory computer-readable medium storing instructions readable by a mobile terminal including a memory, an input interface, a first communication interface and a second communication interface, the instructions causing the mobile terminal to perform processes comprising: a storage processing of storing workflow information including device identification information and action identification information; a specifying processing of specifying the image processing apparatus, as a designated device; an information reception processing of receiving connection information from the designated device through the first communication interface; an extraction processing of extracting the workflow information coinciding with a first condition, among the workflow information; and an execution instruction processing of transmitting execution instruction information to the designated device through the second communication interface by using the connection information, wherein the execution instruction information is to instruct execution of the action identified by the action identification information.

2. 发明授权

US09853910B2 Contents reproduction apparatus 有权
公开(公告)号：US09853910B2
公开(公告)日：2017-12-26
申请号：US15114358
申请日：2015-02-04
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： Michiya Hayama
IPC分类号： H04L12/925 , G01C21/36 , H04L29/08 , H04L13/08 , H04N21/414 , H04N21/44 , H04N21/442
CPC分类号： H04L47/722 , G01C21/36 , G01C21/3629 , H04L13/08 , H04L67/12 , H04L67/18 , H04N21/41422 , H04N21/44004 , H04N21/44209
摘要： A contents reproduction apparatus has a contents buffer, a contents reproduction unit, a navigation function unit that provides guide in a route to a destination, an output switching unit that selects first audio data outputted from the contents reproduction unit or second audio data outputted from the navigation function unit and outputs the selected audio data to outside, and a streaming control unit that sets a buffer size that is a target value of the data amount of contents data to be accumulated in the contents buffer and controls the contents reproduction unit and the output switching unit. When the data amount of contents data accumulated in the contents buffer is less than the buffer size, a reproduction operation of the contents reproduction unit is stopped in a period in which the second audio data are outputted to outside.

3. 发明授权

US07010651B2 System and method for using removable storage for computer troubleshooting 有权
标题翻译：使用可移动存储进行计算机故障排除的系统和方法
公开(公告)号：US07010651B2
公开(公告)日：2006-03-07
申请号：US10603075
申请日：2003-06-23
申请人： Thomas F. McGuffin
发明人： Thomas F. McGuffin
IPC分类号： H04L13/08 , H04L29/08
CPC分类号： G06F11/328
摘要： A computer system monitoring apparatus that collects various system and operating parameters to a removable memory unit. The system includes an operating system controlling at least one process along with a memory for executing operation instructions and a permanent memory storage coupled to the computer. The system monitors the status of a process within the computer, including the process state and any events that occur to alter the state. The system logs the status data of the process within the computer upon a change in the status of the process, accumulates the status data, and writes the status data to the memory storage in a manner to always maintain the most recent system status information on the memory storage. When a fault in the computer system occurs, the memory unit can be retrieved, and the data thereon is used to troubleshoot the fault.
摘要翻译：一种用于向可移动存储器单元收集各种系统和操作参数的计算机系统监视装置。该系统包括操作系统以及用于执行操作指令的存储器以及耦合到计算机的永久存储器存储器来控制至少一个进程。系统监视计算机内进程的状态，包括进程状态以及任何改变状态的事件。系统在过程状态发生变化时记录进程的状态数据，累积状态数据，并将状态数据写入到存储器存储器中，以便始终保持最新的系统状态信息内存存储。当计算机系统发生故障时，可以检索存储器单元，并且使用其上的数据来排除故障。

4. 发明授权

US06978327B1 Data transfer control device and electronic equipment for performing data 失效
标题翻译：用于执行数据的数据传输控制装置和电子设备
公开(公告)号：US06978327B1
公开(公告)日：2005-12-20
申请号：US09787077
申请日：2000-07-12
申请人： Takuya Ishida , Yoshiyuki Kamihara
发明人： Takuya Ishida , Yoshiyuki Kamihara
IPC分类号： G06F13/38 , G06F13/00 , H04L12/28 , H04L12/40 , H04L12/407 , H04L12/64 , H04L13/08 , G06F3/00 , G06F15/16
CPC分类号： H04L12/40052 , H04L12/2801 , H04L12/40071 , H04L12/407
摘要： The objective of the present invention is to provide a data transfer control device that enables a reduction in the processing load on the firmware during the occurrence of a bus reset, and electronic equipment using the same. A data transfer control device in accordance with the IEEE 1394 standard generates a bit BT that toggles whenever one received packet and the next received packet are received in different bus reset intervals, and comprises that BT in the header of each packet stored in RAM. Bus reset pointers (a bus reset header pointer and a bus reset ORB pointer) that indicate a bus reset boundary in RAM are provided, enabling simple differentiation between a packet received before a bus reset occurred and a packet received after the reset. If transmission has been halted by the occurrence of the bus reset, the bus reset transmission halt status is passed to the firmware via a register.
摘要翻译：本发明的目的是提供一种在总线复位发生期间能够减少固件上的处理负荷的数据传送控制装置，以及使用该数据传输控制装置的电子设备。根据IEEE 1394标准的数据传输控制装置产生一个BT，每当一个接收到的分组和下一个接收的分组在不同的总线重置间隔中被接收时，该BT将切换，并且包括存储在RAM中的每个分组的报头中的BT。提供了指示RAM中总线复位边界的总线复位指针（总线复位头指针和总线复位ORB指针），使总线复位发生之前接收到的数据包与复位后接收的数据包之间能够简单区分。如果通过总线复位发生停止传输，则总线复位传输中止状态通过寄存器传递给固件。

5. 发明申请

US20050271070A1 Radio module 审中-公开
标题翻译：无线电模块
公开(公告)号：US20050271070A1
公开(公告)日：2005-12-08
申请号：US11133330
申请日：2005-05-20
申请人： Taro Mikami , Takeshi Yoshida , Suguru Ogawa
发明人： Taro Mikami , Takeshi Yoshida , Suguru Ogawa
IPC分类号： H04L12/801 , H04B7/00 , H04B7/26 , H04L12/879 , H04L12/911 , H04L13/08 , H04M1/725 , H04W4/00 , H04W88/02
CPC分类号： H04N21/23406 , H04M1/72555 , H04N21/6338 , H04N21/64738
摘要： The objective of the invention is the constant optimization of the sizes of buffers required for a transmission process and a reception process, and the effective use of memory resources. A contents processor includes a contents change detector. When the contents are changed, the contents change detector transmits to a wireless communication unit a contents identifier corresponding to contents that are to be newly processed by the wireless communication unit. The wireless communication unit includes a contents information table in which information concerning the contents is stored. The wireless communication unit examines the contents information table, obtains the sizes of buffers required for a transmission process and a reception process, based on the contents identifier transmitted by the contents processor, and redistributes the transmission buffer and the reception buffer for a buffer queue.
摘要翻译：本发明的目标是对传输过程和接收处理所需的缓冲器的大小进行不断的优化，并且有效地使用存储器资源。内容处理器包括内容改变检测器。当内容改变时，内容变更检测器向无线通信单元发送对应于由无线通信单元新处理的内容的内容标识符。无线通信单元包括其中存储有关内容的信息的内容信息表。无线通信单元基于由内容处理器发送的内容标识符，检查内容信息表，获得发送处理和接收处理所需的缓冲器的大小，并重新分配缓冲器队列的发送缓冲器和接收缓冲器。

6. 发明申请

US20050243866A1 Packet transmission apparatus, packet transmission system and packet transmission method 有权
标题翻译：分组传输装置，分组传输系统和分组传输方法
公开(公告)号：US20050243866A1
公开(公告)日：2005-11-03
申请号：US11096762
申请日：2005-03-31
申请人： Hiroshi Koguchi
发明人： Hiroshi Koguchi
IPC分类号： H04J3/16 , H04J3/22 , H04J3/24 , H04L12/28 , H04L12/40 , H04L12/64 , H04L12/951 , H04L13/08 , H04L29/06 , H04L12/56
CPC分类号： H04L12/40071 , H04L12/40084 , H04L69/22
摘要： There is provided a packet transmission apparatus, system and method that are implemented in an apparatus generating a packet to send out packet generated toward another device via a network bus, including: generating a first packet having a first header and contents data; inputting a data string of the first packet to a buffer from its head successively; determining whether the network bus is available in case where a predetermined data sending condition is satisfied; reading out contents data that is input to the buffer and that is not yet read out from the buffer, in case where the network bus is available; generating a second header on the basis of a size of the contents data read out and the first header; adding the second header to the contents data read out to generate a second packet; and outputting the generated second packet to the network bus.
摘要翻译：提供了一种分组发送装置，系统和方法，其在生成分组的装置中实现，以经由网络总线向另一装置发送分组，包括：生成具有第一报头和内容数据的第一分组; 将第一分组的数据串从其头连续地输入到缓冲器; 在满足预定数据发送条件的情况下，确定网络总线是否可用; 在网络总线可用的情况下，读取输入到缓冲器并且尚未从缓冲器读出的内容数据; 基于读出的内容数据的大小和第一标题来生成第二标题; 将第二标题添加到读出的内容数据以产生第二分组; 并将所生成的第二分组输出到网络总线。

7. 发明申请

US20050226147A1 Relay device 有权
标题翻译：继电器
公开(公告)号：US20050226147A1
公开(公告)日：2005-10-13
申请号：US10999932
申请日：2004-12-01
申请人： Toshihiko Nakamura
发明人： Toshihiko Nakamura
IPC分类号： G06F13/28 , H04J3/14 , H04L12/26 , H04L12/28 , H04L12/46 , H04L13/08 , H04L12/56
CPC分类号： H04L47/10 , H04L43/16 , H04L47/30 , H04L47/32
摘要： A data relay device transmitting received unit data has an external interface unit, a main control unit, where the received unit data are received from outside the data relay device and transmitted to the corresponding destination memory not through the main control unit. The external interface unit is equipped with memory in the external interface, the threshold setting unit, and the external control unit. The main control unit receiving the threshold receiving notice reads the information in the corresponding field of the received unit data stored in the memory in the external interface and judges whether the received unit data should be transmitted, or not. The main control unit deletes the received unit data judged to be unnecessary before the transmitting.
摘要翻译：发送接收单元数据的数据中继装置具有外部接口单元，主控单元，其中接收到的单元数据从数据中继设备外部接收并且不通过主控制单元发送到相应的目的地存储器。外部接口单元在外部接口，阈值设置单元和外部控制单元中配有存储器。接收阈值接收通知的主控制单元读取在外部接口中存储在存储器中的接收单元数据的相应字段中的信息，并判断是否应该发送所接收的单元数据。主控制单元在发送之前删除被判断为不必要的接收单元数据。

8. 发明申请

US20050111353A1 Memory management system having a linked list processor 有权
标题翻译：内存管理系统具有链表处理器
公开(公告)号：US20050111353A1
公开(公告)日：2005-05-26
申请号：US10699315
申请日：2003-10-31
申请人： Peter Zievers
发明人： Peter Zievers
IPC分类号： G06F12/02 , G06F12/00 , G06F12/06 , G06F12/08 , G06F13/16 , G06F13/38 , H04L13/08 , H04L1/00
CPC分类号： G06F13/1673 , G06F12/0802
摘要： A memory management system adapted to process linked list data files. The system has a plurality of low storage capacity high speed memories and a lower speed high storage capacity bulk memory. An access flow regulator generates requests for the reading and writing of linked list files by the memories. The head and tail buffers and at any intermediate buffers of a linked list are written into the high speed memories. The intermediate buffers are immediately transferred from the high speed memories to said bulk memory while leaving the head buffer and the tail buffer of the linked list in the high speed memories. In read operations, the head and tail buffers are read from the high speed memories. The intermediate buffers are transferred from the bulk memory to said the high speed memory and then read from the high speed memories.
摘要翻译：适于处理链表的数据文件的存储器管理系统。该系统具有多个低存储容量的高速存储器和较低速度的高存储容量的大容量存储器。访问流量调节器生成由存储器读取和写入链接的列表文件的请求。头尾缓冲器和链表的任何中间缓冲器被写入高速存储器。中间缓冲器立即从高速存储器转移到所述批量存储器，同时将高速存储器中的链接列表的头缓冲器和尾缓冲器留下。在读操作中，从高速存储器读取头和尾缓冲器。中间缓冲器从大容量存储器传送到高速存储器，然后从高速存储器读取。

9. 发明申请

US20050093871A1 Digital line delay using a single port memory 有权
标题翻译：使用单端口内存的数字线路延迟
公开(公告)号：US20050093871A1
公开(公告)日：2005-05-05
申请号：US10490015
申请日：2002-09-19
申请人： Paul Filliman , Michael Knox , David Simpson
发明人： Paul Filliman , Michael Knox , David Simpson
IPC分类号： H04L13/08 , H04N5/04 , H04N5/14 , H04N5/77 , H04N5/775 , H04N5/781 , H04N5/85 , H04N5/907 , H04N9/804 , G06F13/00
CPC分类号： H04N9/8042 , H04N5/04 , H04N5/14 , H04N5/772 , H04N5/775 , H04N5/781 , H04N5/85 , H04N5/907 , H04N7/01
摘要： An apparatus for delaying video line data between a sending device and a receiving device is provided. The apparatus includes a single port random access memory (“RAM”) and a processing arrangement including a first storage device coupled to the RAM and a second storage device coupled to the RAM.
摘要翻译：提供一种用于在发送设备和接收设备之间延迟视频行数据的设备。该装置包括单端口随机存取存储器（“RAM”）和包括耦合到RAM的第一存储装置和耦合到RAM的第二存储装置的处理装置。

10. 发明申请

US20050058071A1 Optical access system 审中-公开
标题翻译：光接入系统
公开(公告)号：US20050058071A1
公开(公告)日：2005-03-17
申请号：US10728107
申请日：2003-12-03
申请人： Katsuhiko Hirashima , Kazuhiro Uchida , Masamichi Kasa , Susumu Tominaga
发明人： Katsuhiko Hirashima , Kazuhiro Uchida , Masamichi Kasa , Susumu Tominaga
IPC分类号： H04B10/27 , H04B10/272 , H04B10/524 , H04L12/26 , H04L12/44 , H04L13/08 , H04Q11/00
CPC分类号： H04Q11/0067 , H04Q11/0071 , H04Q2011/0064
摘要： An optical access system that sends packets in a given time slot more efficiently without wasting bandwidth. The uplink channel from slave devices to a master device is divided into time slots. The sending slave device reads out upstream packets from its send packet buffer when an assigned time slot comes. If the maximum frame size is reached in the middle of a packet, the slave device suspends further reading until a next assigned time slot comes. The packets are sent to the master device, each being set off by a start and end delimiters. Detection of a start delimiter causes the master device to begin writing each received data word into a receive packet buffer, which is terminated by the end delimiter of that packet. Received packets are retrieved from their memory locations specified by a read address that includes the sender's slave device number.
摘要翻译：光接入系统能够更有效地发送给定时隙中的报文，而不会浪费带宽。从从设备到主设备的上行信道分为时隙。当分配的时隙到来时，发送从设备从其发送分组缓冲区读出上行分组。如果在分组中间达到最大帧大小，则从设备将暂停进一步读取，直到下一个分配的时隙到来。这些数据包被发送到主设备，每个设备都由一个起始和终止分隔符来设置。起始分隔符的检测使得主设备开始将每个接收到的数据字写入接收分组缓冲器，接收分组缓冲器由该分组的结束分隔符终止。从包含发送方从设备编号的读取地址指定的存储单元检索接收到的数据包。

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