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1. 发明授权

US11018675B2 Matrix phase interpolator for phase locked loop 有权
公开(公告)号：US11018675B2
公开(公告)日：2021-05-25
申请号：US16566648
申请日：2019-09-10
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
IPC分类号： H03L7/08 , H03L7/087 , H03L7/099 , H04L7/033 , H04L25/14 , H04L25/02 , H04L25/40 , H04L25/493 , H03K19/21 , H03L7/089 , H04L7/00
摘要： Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

2. 发明授权

US10833899B2 Low power physical layer driver topologies 有权
公开(公告)号：US10833899B2
公开(公告)日：2020-11-10
申请号：US16526332
申请日：2019-07-30
申请人： QUALCOMM Incorporated
发明人： Shih-Wei Chou , Chulkyu Lee , Dhaval Sejpal
IPC分类号： H04L25/02 , H04L25/493 , G06F13/40 , H04B1/04 , H04B3/52
摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.

3. 发明授权

US10686443B2 Transmitting device, transmitting method, and communication system 有权
公开(公告)号：US10686443B2
公开(公告)日：2020-06-16
申请号：US16313420
申请日：2017-06-08
申请人： Sony Semiconductor Solutions Corporation
发明人： Takahiro Shimada , Hiroaki Hayashi
IPC分类号： H03K19/0185 , H04L25/493 , H04B3/06 , H04L25/02 , H04L25/49 , H04L25/03 , H03K19/0175 , H03K17/687
摘要： A transmitting device of the present disclosure includes: a voltage generator that generates a predetermined voltage; a first driver including a first sub-driver and a second sub-driver, the first dub-driver that includes a first switch provided on a path from a first power source to a first output terminal, a second switch provided on a path from a second power source to the first output terminal, and a third switch provided on a path from the voltage generator to the first output terminal, and is allowed to set a voltage state of the first output terminal to any of a predetermined number of voltage states which are three or more voltage states, and the second sub-driver that is allowed to adjust a voltage in each of the voltage states of the first output terminal; and a controller that controls an operation of the first driver to perform emphasis.

4. 发明授权

US10511464B2 Baud rate tracking and compensation apparatus and method 有权
公开(公告)号：US10511464B2
公开(公告)日：2019-12-17
申请号：US16128884
申请日：2018-09-12
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Bixing Ye , Zuohui Peng , Chaoming Li , Qin Zhang , Zhilin Wu
IPC分类号： H04L25/493 , H04L7/04 , H04L7/033 , H04L25/02 , H04B10/50 , H04B10/69 , H04B10/60 , H04B10/40
摘要： Disclosed is a baud rate tracking and compensation apparatus comprising: a clock generating component generating a clock; a sampling circuit sampling a reception signal according to the clock and thereby generating a sampled result, and the sampling circuit generating a transition notification signal when the sampled result indicates a transition of the reception signal; a clock counting circuit counting cycles of the clock between a first transition of the reception signal and a second transition of the reception signal according to the clock and the transition notification signal; a bit counting circuit counting bit(s) between the first transition and the second transition according to the clock and a bit cycle; and a calculation circuit dividing the number of the cycles by the number of the bit(s) to obtain a calculation value, and then updating the bit cycle according to the calculation value.

5. 发明授权

US10511463B2 Reception device, reception method, and communication system 有权
公开(公告)号：US10511463B2
公开(公告)日：2019-12-17
申请号：US15752379
申请日：2016-08-12
申请人： Sony Corporation
发明人： Hiroo Takahashi
IPC分类号： H04L25/493 , H04L1/00
摘要： A reception device according to the present disclosure includes: a receiver that generates a symbol signal indicating a sequence of symbols on the basis of a plurality of transmission signals; a transition signal generator that generates a transition signal indicating a sequence of symbol transitions on the basis of the symbol signal; and a converter that repeats an operation of converting transition data including a predetermined number of the symbol transitions into reception data to convert the sequence of the symbol transitions into a sequence of reception data, and generates, in a case where the sequence of the symbol transitions includes first transition data that is not convertible into the reception data, candidate data as a candidate of the reception data on the basis of the first transition data.

6. 发明授权

US10069431B2 Low-skew communication system 有权
公开(公告)号：US10069431B2
公开(公告)日：2018-09-04
申请号：US14894538
申请日：2014-06-17
申请人： Maschinenfabrik Reinhausen GmbH
发明人： Robert John Leedham , Matteo Vit , Stephen Parker , Ivan Cronin
IPC分类号： H04L25/493 , H02M7/00 , H04L12/40 , G06F13/42 , G05B15/02 , H02M1/00
摘要： The invention generally relates to power converters, and more particularly to a communications method for controlling at least one power switching device of a power converter, a communications system for a power converter, and a power converter comprising the communications system. For example there is provided a communications method for controlling at least one power switching device of a power converter, the method comprising: inputting a signal to a transmit end of a communications link; inputting data to the transmit end of the communications link; determining whether the signal comprises a transition; when said determination indicates that the signal comprises a transition, transmitting the signal comprising the transition into a communications channel of the communications link, wherein the transmitted signal is delayed by a predetermined time delay relative to the inputted signal, said predetermined time delay to allow said determining; transmitting the data on the communications channel, wherein when said determination indicates that the signal comprises a transition the transmitting the data is delayed until after said transmitting the signal; and if the signal has been transmitted, receiving the transmitted signal at the receive end of the communications link and controlling at least one said power switching device dependent on said received signal.

7. 发明授权

US09842020B2 Multi-wire symbol transition clocking symbol error correction 有权
公开(公告)号：US09842020B2
公开(公告)日：2017-12-12
申请号：US14949290
申请日：2015-11-23
申请人： QUALCOMM Incorporated
发明人： Shoichiro Sengoku
IPC分类号： H04L25/03 , G06F11/10 , H04L1/00 , H04L27/38 , H03M13/03 , H04L1/24 , H04L25/02 , H04L25/14 , H04L25/493 , H03M5/00 , H03M13/00
CPC分类号： G06F11/1004 , H03M5/00 , H03M13/03 , H03M13/63 , H04L1/004 , H04L1/0041 , H04L1/0061 , H04L1/245 , H04L7/033 , H04L25/0264 , H04L25/0272 , H04L25/03286 , H04L25/14 , H04L25/493 , H04L27/38
摘要： Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver.

8. 发明申请

US20170310529A1 Data Processing Method and Data Processing Apparatus 审中-公开
公开(公告)号：US20170310529A1
公开(公告)日：2017-10-26
申请号：US15644350
申请日：2017-07-07
申请人： Huawei Technologies Co., Ltd.
发明人： Wenbin Yang , Xinyuan Wang , Tongtong Wang
IPC分类号： H04L27/38 , H04L25/493 , H04L1/00
CPC分类号： H04L27/38 , H04B14/023 , H04L1/0045 , H04L1/0071 , H04L25/4917 , H04L25/493
摘要： A data processing method and an apparatus, where the method includes receiving m data streams using m receive ports respectively, where the m data streams include m×m data units, and the m×m data units form an m-order matrix A, keeping a location of one element in each row in the matrix A unchanged and moving remaining m−1 elements to remaining m−1 rows respectively in order to form an m-order matrix B, where a column number of each element in the remaining m−1 elements in the matrix A before the element is moved equals a column number of the element in the remaining m−1 elements in the matrix B after the element is moved, and sending using m transmit ports, the m×m elements in the matrix B to m different levels of a pulse amplitude modulation (PAM) circuit respectively for performing modulation.

9. 发明授权

US09787355B2 System and method for communication using hybrid signals 有权
公开(公告)号：US09787355B2
公开(公告)日：2017-10-10
申请号：US14042475
申请日：2013-09-30
申请人： QUALCOMM Incorporated
发明人： Bin Tian , Gwendolyn Denise Barriac , Sameer Vermani , Hemanth Sampath
IPC分类号： H04B1/00 , H04B1/707 , H04L25/493 , H04L27/00 , H04L27/26 , H04L27/02
CPC分类号： H04B1/707 , H04L25/493 , H04L27/0008 , H04L27/02 , H04L27/2601
摘要： Systems and methods for communication using hybrid signals are disclosed. In one aspect an apparatus for communication includes a processing system configured to encode a first set of information in a plurality of symbols and to encode a second set of information according to a spacing among the symbols. The apparatus may further comprise a transmitter configured to transmit to a device the symbols with the spacing among the symbols. In another aspect, an apparatus for communication includes a processing system configured to decode a first set of information from a plurality of symbols encoded with the first set of information or a second set of information from a spacing among the symbols by determining the spacing among the symbols. The apparatus may further comprise a receiver configured to receive the symbols via a wireless communication.

10. 发明授权

US09667369B2 Interface circuit for transmitting and receiving digital signals between devices 有权
公开(公告)号：US09667369B2
公开(公告)日：2017-05-30
申请号：US14940365
申请日：2015-11-13
申请人： Sony Corporation
发明人： Gen Ichimura , Hidekazu Kikuchi , Yasuhisa Nakajima
IPC分类号： H04L7/00 , H04J3/06 , H04L25/02 , H04L25/493 , H04N21/436 , H04N21/4363 , H04N21/643
CPC分类号： H04L25/0276 , H04J3/0638 , H04J3/0641 , H04L7/0016 , H04L7/0091 , H04L25/0272 , H04L25/0292 , H04L25/493 , H04N21/43615 , H04N21/43635 , H04N21/64322
摘要： A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

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