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1. 发明申请

US20230126011A1 COMPUTER SYSTEM FOR PROCESSING PIXEL DATA OF AN IMAGE 有权
公开(公告)号：US20230126011A1
公开(公告)日：2023-04-27
申请号：US18045097
申请日：2022-10-07
申请人： STMicroelectronics (Rousset) SAS
发明人： Olivier Ferrand , Jean-Francois Link
IPC分类号： G06T1/60 , G06F12/10 , G06F12/0802
摘要： In an embodiment a computer system includes at least one master module configured to process data having a format of N bits, a framebuffer configured to store pixel color component values of an image, the framebuffer having a resolution of N bits, each pixel being coded on P bits in the framebuffer and the pixels being stored one after another in the framebuffer and a memory management unit configured to control memory accesses of the at least one master module to the framebuffer, wherein the memory management unit is further configured to receive read memory access requests from the at least one master module, read at least one pixel in the framebuffer saved on P bits, and modify the format of the at least one read pixel by adding Q additional bits equal to a difference between N and P so as to format the at least one pixel on N bits before transmitting the at least one pixel to the at least one master module.

2. 发明申请

US20230120010A1 DYNAMIC CHUNK SIZE ADJUSTMENT FOR CACHE-AWARE LOAD BALANCING 有权
公开(公告)号：US20230120010A1
公开(公告)日：2023-04-20
申请号：US17503562
申请日：2021-10-18
申请人： Dell Products L.P.
发明人： Rimpesh Patel , Amit Pundalik Anchi , Sanjib Mallick
IPC分类号： G06F12/0802 , G06F3/06
摘要： A method in one embodiment comprises separating logical block addresses of one or more storage devices of a storage system into a plurality of ranges of logical block addresses using a designated chunk size, the chunk size denoting a particular number of logical block addresses. The method further comprises assigning different ones of the ranges of logical block addresses to different ones of a plurality of cache entities of the storage system, to select paths for delivery of respective input-output operations from a host device to the storage system based at least in part on the assigning, detecting particular ones of the input-output operations that each overlap with two or more adjacent ranges of the plurality of ranges, and responsive to the detected input-output operations exceeding a threshold, modifying the chunk size and repeating at least portions of the separating, assigning, selecting and detecting utilizing the modified chunk size.

3. 发明授权

US11631377B2 Timing controller control method and timing controller 有权
公开(公告)号：US11631377B2
公开(公告)日：2023-04-18
申请号：US17421280
申请日：2020-06-10
申请人： BEIHAI HKC OPTOELECTRONICS TECHNOLOGY CO., LTD. , Chongqing HKC Optoelectronics Technology Co., ltd.
发明人： Mingliang Wang
IPC分类号： G06F13/42 , G09G3/36 , G06F13/40 , G06F13/38 , G06F12/0802 , G06F11/10
摘要： The present disclosure relates to a method for controlling a timing controller and a timing controller. The method for controlling the timing controller includes: acquiring a bus address in a bus signal transmitted over an I2C bus, the I2C bus being connected to the timing controller; if the timing controller determining that the bus address matches an address of the timing controller, acquiring data information in the bus signal; acquiring an address of a target function circuit according to the data information; generating and transmitting a query instruction to a memory according to the address of the target function circuit, and receiving switch control data corresponding to the target function circuit fed back by the memory; controlling, according to the switch control data, a switch connected to the target function circuit to be turned on.

4. 发明授权

US11620256B2 Systems and methods for improving cache efficiency and utilization 有权
公开(公告)号：US11620256B2
公开(公告)日：2023-04-04
申请号：US17732308
申请日：2022-04-28
申请人： Intel Corporation
发明人： Altug Koker , Joydeep Ray , Ben Ashbaugh , Jonathan Pearce , Abhishek Appu , Vasanth Ranganathan , Lakshminarayanan Striramassarma , Elmoustapha Ould-Ahmed-Vall , Aravindh Anantaraman , Valentin Andrei , Nicolas Galoppo Von Borries , Varghese George , Yoav Harel , Arthur Hunter, Jr. , Brent Insko , Scott Janus , Pattabhiraman K , Mike Macpherson , Subramaniam Maiyuran , Marian Alin Petre , Murali Ramadoss , Shailesh Shah , Kamal Sinha , Prasoonkumar Surti , Vikranth Vemulapalli
IPC分类号： G06F12/08 , G06F15/78 , G06F9/30 , G06F9/38 , G06F17/18 , G06F12/0802 , G06F7/544 , G06F7/575 , G06F12/02 , G06F12/0866 , G06F12/0875 , G06F12/0895 , G06F12/128 , G06F12/06 , G06F12/1009 , G06T1/20 , G06T1/60 , H03M7/46 , G06F12/0811 , G06F15/80 , G06F17/16 , G06F7/58 , G06F12/0871 , G06F12/0862 , G06F12/0897 , G06F9/50 , G06F12/0804 , G06F12/0882 , G06F12/0891 , G06F12/0893 , G06T15/06 , G06N3/08
摘要： Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

5. 发明申请

US20230103000A1 HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES 有权
公开(公告)号：US20230103000A1
公开(公告)日：2023-03-30
申请号：US17485386
申请日：2021-09-25
申请人： Intel Corporation
发明人： Rupin Vakharwala , Prashant Sethi , Rajesh M. Sankaran , Philip R. Lantz , David J. Harriman , Utkarsh Y. Kakaiya , Vinay Raghav , Ashok Raj , Siva Bhanu Krishna Boga
IPC分类号： G06F12/1027 , G06F12/0802 , G06F13/42
摘要： Embodiments of apparatuses, methods, and systems for hardware manage address translation services are described. In an embodiment, an apparatus includes a first interconnect, a second interconnect, address translation hardware, a device, a translation lookaside buffer. The address translation hardware is coupled to the interconnect and is to provide a translation of a first address to a second address. The device is coupled to the first interconnect and the second interconnect and is to provide the first address to the address translation hardware through the first interconnect. The translation lookaside buffer includes an entry to store the translation, which is to be provided to the translation lookaside buffer through the first interconnect by the address translation hardware. The device is to access a system memory through the second interconnect using the second address from the entry in the translation lookaside buffer. The second interconnect is in the only path between the device and the system memory.

6. 发明申请

US20230095461A1 Using Epoch Counter Values for Controlling the Retention of Cache Blocks in a Cache 有权
公开(公告)号：US20230095461A1
公开(公告)日：2023-03-30
申请号：US17491478
申请日：2021-09-30
申请人： Advanced Micro Devices, Inc.
发明人： Nuwan Jayasena
IPC分类号： G06F12/0802
摘要： An electronic device includes a cache, a memory, and a controller. The controller stores an epoch counter value in metadata for a location in the memory when a cache block evicted from the cache is stored in the location. The controller also controls how the cache block is retained in the cache based at least in part on the epoch counter value when the cache block is subsequently retrieved from the location and stored in the cache.

7. 发明申请

US20230080105A1 NON-VOLATILE STORAGE CONTROLLER WITH PARTIAL LOGICAL-TO-PHYSICAL (L2P) ADDRESS TRANSLATION TABLE 有权
公开(公告)号：US20230080105A1
公开(公告)日：2023-03-16
申请号：US18057726
申请日：2022-11-21
申请人： Innogrit Technologies Co., Ltd.
发明人： Bo FU , Chi-Chun LAI , Jie CHEN , Dishi LAI , Jian WU , Cheng-Yun HSU , Qian CHENG
IPC分类号： G06F12/1045 , G06F12/0802
摘要： Systems, apparatus and methods are provided for logical-to-physical (L2P) address translation. A method may comprise receiving a request for a first logical data address (LDA), and calculating a first translation data unit (TDU) index for a first TDU. The first TDU may contain a L2P entry for the first LDA. The method may further comprise searching a cache of lookup directory entries of recently accessed TDUs using the first TDU index, determining that there is a cache miss, generating and storing an outstanding request for the lookup directory entry for the first TDU in a miss buffer, retrieving the lookup directory entry for the first TDU from an in-memory lookup directory, determining that the lookup directory entry for the first TDU is not valid, reserve a TDU space for the first TDU in a memory and generating a load request for the first TDU.

8. 发明授权

US11599462B1 Memory cache entry management with pinned cache entries 有权
公开(公告)号：US11599462B1
公开(公告)日：2023-03-07
申请号：US17518467
申请日：2021-11-03
申请人： Google LLC
发明人： Amalia Hawkins
IPC分类号： G06F12/08 , G06F12/0802
摘要： Methods and systems for memory cache entry replacement with pinned cache entries. Data structures are maintained for tracking a state of entries of a memory cache. A first data structure includes identifiers for pinned entries of a memory cache. A second data structure includes identifiers for unpinned entries of the memory cache that have been accessed once. A third data structure includes identifiers for unpinned entries of the memory cache that have been accessed more than once. A request to pin an entry is received. A determination is made that an identifier associated with the entry to pin is included in the second data structure or the third data structure. The identifier associated with the pinned entry is added to the first data structure. A detection is made at a time period that one or more entries of the memory cache are to be removed from the memory cache in accordance with an eviction protocol. Identifiers of one or more unpinned entries with state data that satisfies an eviction criterion associated with the eviction protocol are selected from the second data structure and/or the third data structure. The one or more unpinned entries are removed from the memory cache while the pinned entry with corresponding state data is maintained in the memory cache.

9. 发明授权

US11599461B2 Cache memory architecture and management 有权
公开(公告)号：US11599461B2
公开(公告)日：2023-03-07
申请号：US17385257
申请日：2021-07-26
申请人： EMC IP Holding Company LLC
发明人： Michael Scharland , Mark Halstead , Rong Yu , Peng Wu , Benjamin Yoder , Kaustubh Sahasrabudhe
IPC分类号： G06F12/00 , G06F12/0802 , G06F13/20
摘要： Aspects of the present disclosure relate to data cache management. In embodiments, a storage array's memory is provisioned with cache memory, wherein the cache memory includes one or more sets of distinctly sized cache slots. Additionally, a logical storage volume (LSV) is established with at least one logical block address (LBA) group. Further, at least one of the LSV's LBA groups is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array.

10. 发明申请

US20230046354A1 METHOD AND APPARATUS TO REDUCE CACHE STAMPEDING 有权
公开(公告)号：US20230046354A1
公开(公告)日：2023-02-16
申请号：US17880481
申请日：2022-08-03
申请人： Walmart Apollo, LLC
发明人： Raikirat Sohi , Mayur Saxena , Sandeep Singh
IPC分类号： G06F12/0802
摘要： An apparatus comprises a memory having a data cache stored therein and a control circuit operably coupled thereto. The control circuit is configured to update that data cache in accordance with a scheduled update time. In the latter regards, by one approach, the control circuit computes selected entries for the data cache prior to the scheduled update time pursuant to a prioritization scheme to provide a substitute data cache. At the scheduled update time, the control circuit switches the substitute data cache for the data cache such that data queries made subsequent to the scheduled update time access the substitute data cache and not the data cache.

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