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1. 发明授权

US09767989B2 Methods of forming features 有权
公开(公告)号：US09767989B2
公开(公告)日：2017-09-19
申请号：US14938026
申请日：2015-11-11
申请人： SEAGATE TECHNOLOGY LLC
发明人： Sridhar Dubbaka , Sriram Viswanathan , Christina Hutchinson
IPC分类号： H01L21/312 , B44C1/22 , H01J37/32 , G11B5/31 , G11B5/00
CPC分类号： H01J37/32009 , G11B5/3116 , G11B5/3163 , G11B2005/0021 , H01J2237/332 , H01J2237/334
摘要： A method of forming a feature in a void, the method including filling the void having at least one sloped wall with a polymeric material; forming a layer of photoresist over the polymeric material; forming a gap in the layer of photoresist; and etching the polymeric material exposed by the gap in the layer of photoresist to form a feature.

2. 发明授权

US09377689B2 Silicone structure-bearing polymer, negative resist composition, photo-curable dry film, patterning process, and electric/electronic part-protecting film 有权
标题翻译：含有硅氧烷结构的聚合物，负性抗蚀剂组合物，光固化型干膜，图案化工艺以及电子/电子部件保护膜
公开(公告)号：US09377689B2
公开(公告)日：2016-06-28
申请号：US14807072
申请日：2015-07-23
申请人： SHIN-ETSU CHEMICAL CO., LTD.
发明人： Katsuya Takemura , Hiroyuki Urano , Masashi Iio , Takayuki Fujiwara , Koji Hasegawa
IPC分类号： G03F7/075 , C08G77/52 , G03F7/40 , G03F7/38 , C07C39/21 , C09D183/14 , C08L83/14 , H01L21/312 , C08G77/12 , G03F7/16 , G03F7/20 , G03F7/32 , G03F7/038 , G03F7/09 , G03F7/11
CPC分类号： G03F7/0757 , C07C39/21 , C08G77/12 , C08G77/52 , C08L83/14 , C09D183/14 , G03F7/038 , G03F7/0382 , G03F7/09 , G03F7/11 , G03F7/168 , G03F7/2002 , G03F7/2037 , G03F7/32 , G03F7/38 , G03F7/40 , H01L21/312 , H01L21/321
摘要： A silicone structure-bearing polymer comprising recurring units derived from a bis(4-hydroxy-3-allylphenyl) derivative and having a Mw of 3,000-500,000 is provided. A chemically amplified negative resist composition comprising the polymer overcomes the stripping problem that a coating is stripped from metal wirings of Cu or Al, electrodes, and SiN substrates.
摘要翻译：提供了含有衍生自双（4-羟基-3-烯丙基苯基）衍生物并具有3,000-500,000的Mw的重复单元的含硅结构的聚合物。包含该聚合物的化学放大型负性抗蚀剂组合物克服了从Cu或Al，电极和SiN衬底的金属布线剥离涂层的剥离问题。

3. 发明授权

US09291907B2 Methods for forming resist features and arrays of aligned, elongate resist features 有权
标题翻译：用于形成抗蚀剂特征的方法和对准的细长抗蚀剂特征的阵列
公开(公告)号：US09291907B2
公开(公告)日：2016-03-22
申请号：US13475574
申请日：2012-05-18
申请人： Kaveri Jain , Adam L. Olson , William R. Brown , Lijing Gou , Ho Seop Eom , Anton J. deVilliers
发明人： Kaveri Jain , Adam L. Olson , William R. Brown , Lijing Gou , Ho Seop Eom , Anton J. deVilliers
IPC分类号： H01L21/312 , G03F7/38 , G03F7/11 , G03F7/32
CPC分类号： G03F7/38 , G03F7/11 , G03F7/322 , G03F7/325
摘要： Methods of forming resist features, resist patterns, and arrays of aligned, elongate resist features are disclosed. The methods include addition of a compound, e.g., an acid or a base, to at least a lower surface of a resist to alter acidity of at least a segment of one of an exposed, acidic resist region and an unexposed, basic resist region. The alteration, e.g., increase or decrease, in the acidity shifts an acid-base equilibrium to either encourage or discourage development of the segment. Such “chemical proximity correction” techniques may be used to enhance the acidity of an exposed, acidic resist segment, to enhance the basicity of an unexposed, basic resist segment, or to effectively convert an exposed, acidic resist segment to an unexposed, basic resist segment or vice versa. Thus, unwanted line breaks, line merges, or misalignments may be avoided.
摘要翻译：公开了形成抗蚀剂特征，抗蚀剂图案和对准的细长抗蚀剂特征的阵列的方法。所述方法包括向抗蚀剂的至少下表面加入化合物，例如酸或碱，以改变暴露的，酸性的抗蚀剂区域和未曝光的碱性抗蚀剂区域中的至少一段的酸度。酸度中的改变，例如增加或减少，使酸碱平衡发生变化，以促进或阻止该区段的发育。可以使用这种“化学邻近校正”技术来增强暴露的酸性抗蚀剂区段的酸度，以增强未曝光的碱性抗蚀剂区段的碱性，或有效地将暴露的酸性抗蚀剂区段转化为未曝光的碱性抗蚀剂段或反之亦然。因此，可以避免不必要的换行符，行合并或未对齐。

4. 发明授权

US09275872B2 Method for forming stair-step structures 有权
标题翻译：形成阶梯结构的方法
公开(公告)号：US09275872B2
公开(公告)日：2016-03-01
申请号：US14581673
申请日：2014-12-23
申请人： Lam Research Corporation
发明人： Qian Fu , Hyun-Yong Yu
IPC分类号： H01L21/312 , H01L21/308 , H01L21/3213 , H01L27/115 , H01L21/3065 , H01L21/67 , H01L21/02 , H01L21/311
CPC分类号： H01L21/3086 , H01L21/02164 , H01L21/02274 , H01L21/3065 , H01L21/3081 , H01L21/31116 , H01L21/31144 , H01L21/32139 , H01L21/67069 , H01L27/11551 , H01L27/11556
摘要： A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.
摘要翻译：提供了一种在基板中形成台阶结构的方法。在衬底上形成有机掩模。在有机掩模上形成具有顶层和侧壁层的硬掩模。去除硬掩模的侧壁层，同时留下硬掩模的顶层。有机面罩被修剪。衬底被蚀刻。重复多次形成硬掩模，去除侧壁层，修整有机掩模和蚀刻基板。

5. 发明授权

US09159577B2 Method of forming substrate pattern 有权
标题翻译：形成基板图案的方法
公开(公告)号：US09159577B2
公开(公告)日：2015-10-13
申请号：US14180409
申请日：2014-02-14
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Chun-Yu Lin , Feng-Yuan Chiu , Bing-Syun Yeh , Yi-Jie Chen , Ying-Chou Cheng , I-Chang Shih , Ru-Gun Liu , Shih-Ming Chang
IPC分类号： H01L21/308 , H01L21/306 , H01L21/311 , H01L21/312 , H01L21/033 , H01L21/3065 , G03F1/36
CPC分类号： H01L21/312 , G03F1/36 , H01L21/0274 , H01L21/3083 , H01L21/31144
摘要： According to an exemplary embodiment, a method of forming a substrate pattern having an isolated region and a dense region is provided. The method includes the following operations: forming a first photoresist layer over the substrate; exposing the first photoresist layer through a first mask corresponding to the isolated region; developing the first photoresist layer to form a first pattern; forming a second photoresist layer over the substrate and the first pattern; exposing the second photoresist layer through a second mask corresponding to the substrate pattern; developing the second photoresist layer to form a second pattern; and etching the first pattern and the substrate to form the substrate pattern in the isolated region and the dense region.
摘要翻译：根据示例性实施例，提供了形成具有隔离区域和致密区域的衬底图案的方法。该方法包括以下操作：在衬底上形成第一光致抗蚀剂层; 通过对应于所述隔离区域的第一掩模曝光所述第一光致抗蚀剂层; 显影第一光致抗蚀剂层以形成第一图案; 在所述衬底和所述第一图案上形成第二光致抗蚀剂层; 通过对应于衬底图案的第二掩模曝光第二光致抗蚀剂层; 显影第二光致抗蚀剂层以形成第二图案; 并且蚀刻第一图案和基板以在隔离区域和致密区域中形成基板图案。

6. 发明授权

US09128384B2 Method of forming a pattern 有权
标题翻译：形成图案的方法
公开(公告)号：US09128384B2
公开(公告)日：2015-09-08
申请号：US13673729
申请日：2012-11-09
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yu Chao Lin , Chia-Hao Hsu , Kuo-Yu Wu , Chia-Jen Chen , Chao-Cheng Chen
IPC分类号： H01L21/66 , H01L21/312 , G03F7/40 , G03F7/00 , G03F7/075 , G03F7/09 , G03F7/095 , H01L21/033 , H01L21/3213
CPC分类号： H01L22/12 , G03F7/0035 , G03F7/0752 , G03F7/091 , G03F7/095 , G03F7/40 , G03F7/70633 , H01L21/0276 , H01L21/0337 , H01L21/31144 , H01L21/32139
摘要： An embodiment of a method of forming a substrate pattern including forming a bottom layer and an overlying middle layer on the substrate. A photo resist pattern is formed on the middle layer. An etch coating layer is deposited on the photo resist pattern. The etch coating layer and the photo resist pattern are used as a masking element to pattern at least one of the middle layer and the bottom layer. The substrate is etched to form the substrate pattern using the at least one of the patterned middle layer and the patterned bottom layer as a masking element. The substrate pattern may be used as an element of an overlay measurement process.
摘要翻译：一种形成衬底图案的方法的实施例，包括在衬底上形成底层和上覆中间层。在中间层上形成光刻胶图形。蚀刻涂层沉积在光刻胶图案上。蚀刻涂层和光刻胶图案用作屏蔽元件以图案化中间层和底层中的至少一个。使用图案化中间层和图案化底层中的至少一个作为掩模元件来蚀刻衬底以形成衬底图案。衬底图案可以用作覆盖测量过程的元件。

7. 发明授权

US09091873B2 Apparatus and method of fabricating thin film pattern 有权
标题翻译：制造薄膜图案的装置和方法
公开(公告)号：US09091873B2
公开(公告)日：2015-07-28
申请号：US13096614
申请日：2011-04-28
申请人： Jin Wuk Kim
发明人： Jin Wuk Kim
IPC分类号： G02F1/1333 , H01L21/02 , H01L21/312 , H01L21/67 , H01L51/56 , H01L27/12
CPC分类号： G02F1/1333 , G02F2202/022 , G02F2202/28 , H01J2209/02 , H01L21/0212 , H01L21/02288 , H01L21/3127 , H01L21/6715 , H01L27/124 , H01L27/1292 , H01L51/56
摘要： A fabricating method and apparatus of a thin film pattern improves the reliability of forming the thin film pattern by a resist printing method. The apparatus includes a print roller device of a roll shape around which a blanket is wound; a spray device located around the print roller device for spraying an etch resist solution to the blanket; and a print plate of an engraved shape where a groove of a desired thin film shape and a projected part except the groove are formed, and the etch resist solution has a surfactant inclusive of an ethylene oxide fluorinated polymer material.
摘要翻译：薄膜图案的制造方法和装置通过抗蚀剂印刷方法提高了形成薄膜图案的可靠性。该装置包括一卷筒形的打印辊装置，一个毯子被卷绕在该辊子上; 位于印刷辊装置周围的喷涂装置，用于将抗蚀剂溶液喷涂到橡皮布上; 以及雕刻形状的印版，其中形成所需薄膜形状的凹槽和除了凹槽之外的突出部分，并且所述蚀刻抗蚀剂溶液具有包含环氧乙烷氟化聚合物材料的表面活性剂。

8. 发明授权

US09048445B2 Gate insulating material, gate insulating film and organic field-effect transistor 有权
标题翻译：栅极绝缘材料，栅极绝缘膜和有机场效应晶体管
公开(公告)号：US09048445B2
公开(公告)日：2015-06-02
申请号：US12933417
申请日：2009-02-27
申请人： Seiichiro Murase , Takenori Fujiwara , Yukari Jo , Jun Tsukamoto
发明人： Seiichiro Murase , Takenori Fujiwara , Yukari Jo , Jun Tsukamoto
IPC分类号： H01L29/78 , H01L51/05 , C08G59/30 , C08G59/32 , C08G65/20 , C08G77/14 , C09D163/00 , H01L21/02 , H01L21/312 , G03F7/075 , H01B3/40 , H01B3/46 , H01L51/00
CPC分类号： H01L51/052 , C08G59/306 , C08G59/3281 , C08G65/20 , C08G77/14 , C09D163/00 , G03F7/0757 , H01B3/40 , H01B3/46 , H01L21/02126 , H01L21/02216 , H01L21/02282 , H01L21/3122 , H01L51/0036 , H01L51/0068 , H01L51/0545
摘要： To provide a gate insulating material which has high chemical resistance, is superior in coatability of a resist and an organic semiconductor coating liquid, and has small hysteresis, a gate insulating film and an FET using the same by a polysiloxane having an epoxy group-containing silane compound as a copolymerization component.A gate insulating material containing a polysiloxane having, as copolymerization components, at least a silane compound represented by the general formula (1): R1mSi(OR2)4-m (1), wherein R1 represents hydrogen, an alkyl group, a cycloalkyl group, a heterocyclic group, an aryl group, a heteroaryl group or an alkenyl group and in the case where a plurality of R1s are present, R1s may be the same or different, R2 represents an alkyl group or a cycloalkyl group and in the case where a plurality of R2s are present, R2s may be the same or different, and m represents an integer of 1 to 3, and an epoxy group-containing silane compound represented by the general formula (2): R3nR4lSi(OR5)4-n-1 (2), wherein R3 represents an alkyl group or a cycloalkyl group having one or more epoxy groups in a part of a chain and in the case where a plurality of R3s are present, R3s may be the same or different, R4 represents hydrogen, an alkyl group, a cycloalkyl group, a heterocyclic group, an aryl group, a heteroaryl group or an alkenyl group and in the case where a plurality of R4s are present, R4s may be the same or different, R5 represents an alkyl group or a cycloalkyl group and in the case where a plurality of R5s are present, R5s may be the same or different, l represents an integer of 0 to 2, and n represents 1 or 2 (however, l+n≦3).
摘要翻译：为了提供耐化学性高的栅极绝缘材料，具有优异的抗蚀剂和有机半导体涂布液的涂布性，并且具有较小的滞后性，栅极绝缘膜和使用该绝缘材料的FET通过具有含环氧基的聚硅氧烷硅烷化合物作为共聚成分。含有作为共聚成分的至少一种由通式（1）表示的硅烷化合物的聚硅氧烷的栅绝缘材料：R1mSi（OR2）4-m（1），其中R1表示氢，烷基，环烷基，杂环基，芳基，杂芳基或烯基，在存在多个R 1的情况下，R 1可以相同或不同，R 2表示烷基或环烷基，在存在多个R 2，R 2可以相同或不同，m表示1〜3的整数，和由通式（2）表示的含环氧基的硅烷化合物：R3nR4lSi（OR5）4-n- 1（2）其中R3表示一部分链中具有一个或多个环氧基的烷基或环烷基，在存在多个R 3的情况下，R 3可以相同或不同，R 4表示氢，烷基，环烷基，杂环基，芳基g 稠环，杂芳基或烯基，在存在多个R 4的情况下，R 4可以相同或不同，R 5表示烷基或环烷基，在存在多个R 5的情况下， R5可以相同或不同，l表示0〜2的整数，n表示1或2（然而，l + n＆nlE; 3）。

9. 发明授权

US08987050B1 Method and system for backside dielectric patterning for wafer warpage and stress control 有权
标题翻译：用于晶片翘曲和应力控制的背面电介质图案化方法和系统
公开(公告)号：US08987050B1
公开(公告)日：2015-03-24
申请号：US13690817
申请日：2012-11-30
申请人： David Jon Hiner , Ronald Patrick Huemoeller , Michael G. Kelly
发明人： David Jon Hiner , Ronald Patrick Huemoeller , Michael G. Kelly
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L21/312 , H01L21/31 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L21/31 , H01L21/312 , H01L21/486 , H01L21/50 , H01L21/6835 , H01L23/147 , H01L23/3171 , H01L23/3192 , H01L23/3675 , H01L23/48 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/14 , H01L24/16 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2221/68327 , H01L2221/6834 , H01L2221/68345 , H01L2224/02372 , H01L2224/03002 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/73253 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/1421 , H01L2924/1433 , H01L2924/14335 , H01L2924/15311 , H01L2924/157 , H01L2924/15788 , H01L2924/1616 , H01L2924/16251 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3511 , H01L2224/11 , H01L2224/03
摘要： Methods and systems for backside dielectric patterning for wafer warpage and stress control are disclosed and may include thinning a semiconductor wafer comprising one or more through silicon vias (TSVs) and one or more die to expose the TSVs on a first surface of the wafer. The wafer may be passivated by depositing dielectric layers. The passivated wafer may be planarized and portions dielectric layers may be selectively removed to reduce a strain on the wafer. Metal contacts may be placed on the exposed TSVs prior to or after the selectively removal. The die may comprise functional electronic die or interposer die. Portions of the dielectric layers may be selectively removed in a radial pattern and may comprise a nitride and/or silicon dioxide layer. The wafer may be thinned to below a top surface of the TSVs. The dielectric layers may be selectively removed utilizing a dry etch process.
摘要翻译：公开了用于晶片翘曲和应力控制的背面电介质图案化的方法和系统，并且可以包括使包括一个或多个通孔（TSV）和一个或多个管芯的半导体晶片变薄以暴露晶片的第一表面上的TSV。可以通过沉积介电层来钝化晶片。钝化的晶片可以被平坦化，并且可以选择性地去除部分电介质层以减小晶片上的应变。可以在选择性移除之前或之后将金属触点放置在暴露的TSV上。芯片可以包括功能电子管芯或插入件管芯。可以以径向图案选择性地去除介电层的一部分，并且可以包括氮化物和/或二氧化硅层。晶片可以变薄到TSV的顶表面之下。可以使用干蚀刻工艺来选择性地去除电介质层。

10. 发明授权

US08969199B1 Methods of forming a circuit that includes a cross-coupling gate contact structure wherein the circuit is to be manufactured using a triple patterning process 有权
标题翻译：形成包括交叉耦合栅极接触结构的电路的方法，其中电路将使用三重图案化工艺制造
公开(公告)号：US08969199B1
公开(公告)日：2015-03-03
申请号：US14054251
申请日：2013-10-15
申请人： Globalfoundries Inc.
发明人： Lei Yuan , Jason Eugene Stephens , Li Yang , Soo Han Choi
IPC分类号： H01L21/312 , H01L21/033 , H01L21/768
CPC分类号： H01L21/0334 , H01L21/31144 , H01L21/76895 , H01L27/0207 , H01L27/11807 , H01L2027/11859
摘要： One illustrative method disclosed herein includes, among other things, patterning a hard mask layer using three patterned photoresist etch masks, wherein a first feature corresponding to a portion, but not all, of a cross-coupling gate contact structure is present in a first of the three patterned photoresist etch masks and a second feature corresponding to a portion, but not all, of the cross-coupling gate contact structure is present in a second or a third of the three patterned photoresist etch masks, patterning a layer of insulating material using the patterned hard mask layer as an etch mask, and forming a cross-coupling gate contact structure in a trench in the layer of insulating material.
摘要翻译：本文公开的一种说明性方法包括使用三种图案化的光致抗蚀剂蚀刻掩模图案化硬掩模层，其中对应于交叉耦合栅极接触结构的一部分但不是全部的第一特征存在于第一三个图案化的光致抗蚀剂蚀刻掩模和对应于交叉耦合栅极接触结构的一部分但不是全部的第二特征存在于三个图案化的光致抗蚀剂蚀刻掩模的第二或第三个中，使用图案化的硬掩模层作为蚀刻掩模，并且在绝缘材料层中的沟槽中形成交叉耦合栅极接触结构。

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