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1. 发明授权

US11430819B2 Array substrate and manufacturing method thereof 有权
公开(公告)号：US11430819B2
公开(公告)日：2022-08-30
申请号：US16761913
申请日：2020-04-24
申请人： TCL China Star Optoelectronics Technology Co., Ltd.
发明人： Weina Yong
IPC分类号： H01L27/12 , H01L29/786 , H01L29/66 , H01L21/8236 , G02F1/1345 , G02F1/1368 , G03F1/32 , G03F1/70 , G03F7/039 , G03F7/40
摘要： The present invention provides an array substrate and a manufacturing method thereof. The manufacturing method of the array substrate adopts a multi-stage mask to expose and develop, so that a thickness of a remaining photoresist layer in a channel region corresponding to a display region is same as a thickness of a remaining photoresist layer in a channel region corresponding to a GOA region. Therefore, the two channel regions can be completely etched to prevent short-circuiting, and make up for defects of different action efficiency of developers caused by different densities of thin film transistors in the display region and the GOA region.

2. 发明申请

US20210376161A1 INVERTER EMPOLYING THIN-FILM TRASISTOR FABRICATED BY ADJUSTING SILICON CONTENT AND METHOD FOR MANUFACTURING SAME 有权
公开(公告)号：US20210376161A1
公开(公告)日：2021-12-02
申请号：US17277998
申请日：2019-09-19
申请人： CHEONGJU UNIVERSITY INDUSTRY & ACADEMY COOPERATION FOUNDATION
发明人： Sang Yeol LEE
IPC分类号： H01L29/786 , H01L27/088 , H01L21/8236 , H02M7/537
摘要： The present invention relates to an inverter employing a thin film transistor fabricated by adjusting a silicon content and a method for manufacturing the same, and the inverter employing a thin film transistor fabricated by adjusting a silicon content includes a depletion mode transistor including a first gate electrode formed on a substrate, a first insulating layer formed on the first gate electrode, and a first source electrode, a first drain electrode, and a first channel layer formed on the first insulating layer, an enhancement mode transistor including a second gate electrode formed on the substrate, a second insulating layer formed on the second gate electrode, and a second source electrode, a second drain electrode, and a second channel layer formed on the second insulating layer; and a wiring unit electrically connecting the electrodes, and the first channel layer and the second channel layer are formed of amorphous silicon oxide layers having different silicon contents. According to the present invention, an inverter may be configured by adjusting a silicon content of a channel layer with the same electrode layer, only using an oxide thin film transistor of an n channel layer in a CMOS including both a p channel layer and an n channel layer to cause a difference in a threshold voltage.

3. 发明申请

US20210143281A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20210143281A1
公开(公告)日：2021-05-13
申请号：US17010151
申请日：2020-09-02
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei YAMAZAKI , Jun KOYAMA , Hiroyuki MIYAKE , Kei TAKAHASHI , Kouhei TOYOTAKA , Masashi TSUBUKU , Kosei NODA , Hideaki KUWABARA
IPC分类号： H01L29/786 , H01L27/12 , H01L29/26 , G06K19/077 , H01L21/8236 , H01L23/66 , H01L27/088 , H01L29/24 , H01L29/66
摘要： An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

4. 发明授权

US10804367B2 Gate stacks for stack-fin channel I/O devices and nanowire channel core devices 有权
公开(公告)号：US10804367B2
公开(公告)日：2020-10-13
申请号：US15719686
申请日：2017-09-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chao-Ching Cheng , Wei-Sheng Yun , I-Sheng Chen , Shao-Ming Yu , Tzu-Chiang Chen , Chih Chieh Yeh
IPC分类号： H01L29/165 , H01L21/8236 , H01L27/092 , H01L29/51 , H01L29/66 , H01L29/10 , H01L27/06 , H01L29/06 , H01L21/8238 , H01L29/775 , H01L29/40
摘要： A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

5. 发明申请

US20200243518A1 HEMT POWER DEVICE OPERATING IN ENHANCEMENT MODE AND MANUFACTURING PROCESS THEREOF 审中-公开
公开(公告)号：US20200243518A1
公开(公告)日：2020-07-30
申请号：US16775843
申请日：2020-01-29
申请人： STMICROELECTRONICS S.r.l.
发明人： Davide Giuseppe PATTI
IPC分类号： H01L27/088 , H01L29/20 , H01L29/205 , H01L29/16 , H01L29/778 , H01L29/78 , H01L29/66 , H01L21/8236 , H01L21/8258 , H03K17/687
摘要： The power device is formed by a D-mode HEMT and by a MOSFET in cascade to each other and integrated in a chip having a base body and a heterostructure layer on the base body. The D-mode HEMT includes a channel area formed in the heterostructure layer; the MOSFET includes a first and a second conduction region formed in the base body, and an insulated-gate region formed in the heterostructure layer, laterally and electrically insulated from the D-mode HEMT. A first metal region extends through the heterostructure layer, laterally to the channel area and in electrical contact with the channel area and the first conduction region.

6. 发明授权

US10707204B2 Composite semiconductor device 有权
公开(公告)号：US10707204B2
公开(公告)日：2020-07-07
申请号：US15742474
申请日：2016-03-31
申请人： SHARP KABUSHIKI KAISHA
发明人： Seiichiro Kihara
IPC分类号： H01L27/088 , H01L29/417 , H01L23/00 , H01L29/78 , H01L29/812 , H01L21/8236 , H01L27/095 , H01L27/06 , H01L29/866 , H01L29/06
摘要： A composite semiconductor device with improved response performance and reliability is provided while an increase in wiring area being suppressed. Fingers 1 are arranged in a plurality of rows and a plurality of columns. A signal inputted via a gate terminal (3) is supplied from intermediate regions in a row-wise direction of gate wires (18) connected to gate electrodes (G) of the same row or two adjacent rows of fingers 1 of the fingers 1 and formed along the rows.

7. 发明授权

US09634118B2 Methods of forming semiconductor devices 有权
公开(公告)号：US09634118B2
公开(公告)日：2017-04-25
申请号：US15164160
申请日：2016-05-25
申请人： Samsung Electronics Co., Ltd.
发明人： Ju-Youn Kim
IPC分类号： H01L21/8236 , H01L21/8238 , H01L29/66 , H01L29/49
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/28185 , H01L21/82345 , H01L21/823821 , H01L21/823842 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming first and second dielectric layers in first and second trenches. The method includes forming first and second conductive layers on the first and second dielectric layers, respectively. The method includes forming first and second protective layers on the first and second conductive layers, respectively. The method includes performing an annealing process while the first and second protective layers are on the first and second conductive layers. The method includes removing the first and second protective layers. The method includes removing the first conductive layer, after performing the annealing process. Moreover, the method includes forming first and second gate metals in the first and second trenches, respectively, after removing the first conductive layer.

8. 发明申请

US20170062419A1 SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS 审中-公开
标题翻译：半导体器件及相关方法
公开(公告)号：US20170062419A1
公开(公告)日：2017-03-02
申请号：US15233785
申请日：2016-08-10
申请人： NXP B.V.
发明人： Matthias Rose , Jan Sonsky
IPC分类号： H01L27/088 , H01L29/16 , H02M3/158 , H01L29/872 , H01L21/8236 , H01L29/20 , H01L27/02
CPC分类号： H01L27/0883 , H01L21/8236 , H01L27/0255 , H01L29/1608 , H01L29/2003 , H01L29/42316 , H01L29/513 , H01L29/778 , H01L29/872 , H02M3/158 , H03K17/6871
摘要： A semiconductor device comprising: a die-source-terminal, a die-drain-terminal and a die-gate-terminal; a semiconductor-die; an insulated-gate-depletion-mode-transistor provided on the semiconductor-die, the insulated-gate-depletion-mode-transistor comprising a depletion-source-terminal, a depletion-drain-terminal and a depletion-gate-terminal, wherein the depletion-drain-terminal is coupled to the die-drain-terminal and the depletion-gate-terminal is coupled to the die-source-terminal; an enhancement-mode-transistor comprising an enhancement-source-terminal, an enhancement-drain-terminal and an enhancement-gate-terminal, wherein the enhancement-source-terminal is coupled to the die-source-terminal, the enhancement-gate-terminal is coupled to the die-gate-terminal and the enhancement-drain-terminal is coupled to the depletion-source-terminal; and a clamp-circuit coupled between the depletion-source-terminal and the depletion-gate-terminal.
摘要翻译：一种半导体器件，包括：芯片 - 源极端子，芯片 - 漏极端子和晶体管 - 栅极端子; 半导体芯片; 设置在所述半导体管芯上的绝缘栅极耗尽型晶体管，所述绝缘栅极耗尽型晶体管包括耗尽源极端子，耗尽 - 漏极端子和耗尽栅极端子，其中耗尽漏极端子耦合到管芯漏极端子，耗尽栅极端子耦合到管芯源极端子; 增强型晶体管，其包括增强源极端子，增强型 - 漏极端子和增强型栅极端子，其中所述增强源极端子耦合到所述管芯源极端子，所述增强型 - 端子耦合到晶体管栅极端子，并且增强漏极端子耦合到耗尽源极端子; 以及耦合在耗尽源极端与耗尽栅极端子之间的钳位电路。

9. 发明授权

US09455331B1 Method and structure of forming controllable unmerged epitaxial material 有权
标题翻译：形成可控非掺杂外延材料的方法和结构
公开(公告)号：US09455331B1
公开(公告)日：2016-09-27
申请号：US14796646
申请日：2015-07-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES INC.
发明人： Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz , Ruilong Xie , Tenko Yamashita
IPC分类号： H01L21/8236 , H01L29/66 , H01L29/78 , H01L29/417 , H01L29/06
CPC分类号： H01L27/0886 , H01L27/0207 , H01L29/0649 , H01L29/41791 , H01L29/6656 , H01L29/66795 , H01L29/6681 , H01L29/7848 , H01L29/785
摘要： A method of forming a semiconductor device that includes forming a plurality of semiconductor pillars. A dielectric spacer is formed between at least one set of adjacent semiconductor pillars. Semiconductor material is epitaxially formed on sidewalls of the adjacent semiconductor pillars, wherein the dielectric spacer obstructs a first portion of epitaxial semiconductor material formed on a first semiconductor pillar from merging with a second portion of epitaxial semiconductor material formed on a second semiconductor pillar.
摘要翻译：一种形成包括形成多个半导体柱的半导体器件的方法。在至少一组相邻的半导体柱之间形成介电间隔物。半导体材料外延地形成在相邻半导体柱的侧壁上，其中电介质间隔物阻挡形成在第一半导体柱上的外延半导体材料的第一部分与形成在第二半导体柱上的第二部分外延半导体材料合并。

10. 发明授权

US09418992B2 High performance power cell for RF power amplifier 有权
标题翻译：用于射频功率放大器的高性能功率单元
公开(公告)号：US09418992B2
公开(公告)日：2016-08-16
申请号：US15063310
申请日：2016-03-07
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Jun-De Jin , Tzu-Jin Yeh , Chewn-Pu Jou
IPC分类号： H01L27/088 , H01L21/8236 , H01L29/66 , H01L29/812 , H01L29/78 , H01L29/06
CPC分类号： H01L27/0883 , H01L21/8236 , H01L21/8238 , H01L21/823821 , H01L21/823828 , H01L21/823885 , H01L27/092 , H01L27/0922 , H01L27/095 , H01L29/0649 , H01L29/66666 , H01L29/66848 , H01L29/7827 , H01L29/812 , H03F1/223 , H03F3/213
摘要： A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the Schottky MOSFET. The source node of the enhancement MOSFET and source node of the Schottky MOSFET are connected together to form the power cell.
摘要翻译：为RF功率放大器设计的功率单元包括形成在P基板中的P阱中的增强型MOSFET和形成在相同P基板中的N阱中的肖特基MOSFET，源极之间具有水平或垂直通道，漏极和栅电极。增强型MOSFET的源节点和肖特基MOSFET的源极节点连接在一起形成功率单元。

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