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1. 发明授权

US11465511B2 Systems and methods to determine and validate torque of an electric machine 有权
公开(公告)号：US11465511B2
公开(公告)日：2022-10-11
申请号：US16742276
申请日：2020-01-14
申请人： FORD GLOBAL TECHNOLOGIES, LLC
发明人： John Proietty , Susan Rebecca Cikanek , Bader M. Badreddine , William Reynolds , Matthew Allan Herrmann
IPC分类号： B60L15/02 , B60W10/08 , H02P6/08 , H02P6/16 , H02P21/22 , H03M1/48 , H02P21/20
摘要： A vehicle includes a multi-core processor having first, second, and cores and having first and second analog-to-digital converters (ADC) associated with the first and second cores, respectively. The first and second ADC are configured to convert analog phase currents to first and second digital phase current values, respectively. The multi-core processor is configured to generate first and second rotor-angle data from digital signals representing a position of the electric machine. The processor is programmed to, via the first core, estimate a first output torque of the electric machine based on the first rotor-angle data and the first digital phase current values, via the second core, estimate a second output torque based on the second rotor-angle data and the second digital phase current values, and, via the third core, command de-activation of the electric machine in response to a difference between the first and second output torques exceeding a threshold.

2. 发明授权

US10996634B2 System and method for fast-converging digital-to-time converter (DTC) gain calibration for DTC-based analog fractional-N phase lock loop (PLL) 有权
$System and method for fast-converging digital-to-time converter (DTC) gain calibration for DTC-based analog fractional-N phase lock loop (PLL)$
公开(公告)号：US10996634B2
公开(公告)日：2021-05-04
申请号：US16040963
申请日：2018-07-20
申请人： Samsung Electronics Co., Ltd.
发明人： Chih-Wei Yao , Ronghua Ni
IPC分类号： G04F10/00 , H03L7/091 , H03M1/12 , H03L7/089 , H03L7/099 , H03M1/48
摘要： A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.

3. 发明授权

US10830798B2 Voltage variation detection circuit, semiconductor integrated circuit, and vehicle 有权
公开(公告)号：US10830798B2
公开(公告)日：2020-11-10
申请号：US15834241
申请日：2017-12-07
申请人： Rohm Co., Ltd.
发明人： Takayuki Nakashima
IPC分类号： G01R19/165 , H03K5/24 , H03K5/02 , G01R19/257 , H03M1/48
摘要： The voltage variation detection circuit includes: a threshold voltage generation circuit arranged to generate a threshold voltage; a comparator arranged to compare a variation detection-target voltage and the threshold voltage to each other; and a controller arranged to control the threshold voltage generation circuit based on output of the comparator. Repeated are operations of: decreasing the threshold voltage stepwise; when the variation detection-target voltage has come to the threshold voltage or more, first increasing the threshold voltage by specified steps and then again decreasing the threshold voltage stepwise; and when the variation detection-target voltage has come to the threshold voltage or more, increasing the threshold voltage by specified steps. The controller detects a variation of the variation detection-target voltage based on control results at time points when the variation detection-target voltage comes to the threshold voltage or more.

4. 发明申请

US20200348626A1 SYSTEM AND METHOD FOR FAST-CONVERGING DIGITAL-TO-TIME CONVERTER (DTC) GAIN CALIBRATION FOR DTC-BASED ANALOG FRACTIONAL-N PHASE LOCK LOOP (PLL) 审中-公开
公开(公告)号：US20200348626A1
公开(公告)日：2020-11-05
申请号：US16935827
申请日：2020-07-22
申请人： Samsung Electronics Co., Ltd.
发明人： Chih-Wei YAO , Ronghua NI
IPC分类号： G04F10/00 , H03L7/091 , H03L7/089 , H03M1/48 , H03L7/099 , H03M1/12
摘要： A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.

5. 发明授权

US10284219B2 Inbuilt threshold comparator 有权
公开(公告)号：US10284219B2
公开(公告)日：2019-05-07
申请号：US16139113
申请日：2018-09-24
申请人： Texas Instruments Incorporated
发明人： Rishi Soundararajan
IPC分类号： H03M1/12 , H03M1/46 , H03K5/24 , H03M1/06 , H03M1/48 , H03M1/44 , H03M1/36
摘要： A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.

6. 发明授权

US10084472B1 Phase modulation-type redundant two-phase-output resolver and signal output method thereof 有权
公开(公告)号：US10084472B1
公开(公告)日：2018-09-25
申请号：US15909248
申请日：2018-03-01
申请人： TAMAGAWA SEIKI CO., LTD.
发明人： Hiroshi Kushihara , Kazuyuki Ishibashi , Hirofumi Maruyama , Katsutoshi Toyotake , Shinichi Arai , Toshiki Muramatsu
IPC分类号： H03M1/48 , H02K24/00 , G01P3/44 , H02P6/16 , G01D5/20 , G01R31/28 , G01D5/244
CPC分类号： H03M1/485 , G01D3/08 , G01D5/2046 , G01D5/2073 , G01D5/24457 , G01D5/2448 , G01P3/44 , G01P3/488 , G01R31/2829 , H02K24/00 , H02P6/16
摘要： The present invention relates to a phase modulation-type redundant two-phase-output resolver, an excitation signal (100) is applied to an excitation winding (50) of an annular stator (21) having a VR-type rotor (20) disposed therein, and a two-phase output signal (101) is outputted from first and second output windings (43, 44) that are provided in the annular stator (21), the excitation winding (50) is made up of first and second excitation windings (40, 41) of mutually different phases, and the excitation signal (100) has two phases, and even in a case where a break occurs in only any one winding from among the first and second excitation windings (40, 41) and the first and second output windings (43, 44), at least a one-phase output signal can be obtained.

7. 发明申请

US20180097465A1 SEMICONDUCTOR DEVICE, MOTOR CONTROL SYSTEM, AND CONTROL METHOD FOR SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180097465A1
公开(公告)日：2018-04-05
申请号：US15719474
申请日：2017-09-28
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Yusuke YASUDA
IPC分类号： H02P29/024 , H02P27/08 , H03M1/48 , G01D5/20
CPC分类号： H02P29/024 , G01D3/08 , G01D5/20 , H02P27/085 , H03M1/485
摘要： A semiconductor device according to one embodiment selects one of the first and second resolver/digital converters and interrupts a supply of a power supply voltage to the other one of the first and second resolver/digital converters, and when an error is detected in the selected one of the first and second resolver/digital converters, the semiconductor device starts the supply of the voltage to the other one of the first and second resolver/digital converters, and switches the one of the first and second resolver/digital converters to the other one of the first and second resolver/digital converters.

8. 发明申请

US20160332307A1 Compact Resolver Pre-Amplification Assembly (RPA) Module 审中-公开
标题翻译：小型旋转变压器前置放大组件（RPA）模块
公开(公告)号：US20160332307A1
公开(公告)日：2016-11-17
申请号：US15153413
申请日：2016-05-12
申请人： THE GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF THE NAVY
发明人： Eric Rossland , Mark Fratta , Greg Levanas
IPC分类号： B25J13/08 , H03M1/48
CPC分类号： B25J13/088 , G01D3/036 , G01D5/2073 , H03M1/485
摘要： A compact resolver pre-amplification assembly has first and second printed circuit boards. The boards include an interface with an N/N−1 resolver and a resolver-to-digital converter and three signal paths. The first and second circuit boards are contained in a single package configured for mounting on a robotic joint while providing high amplification and noise rejection. Low level sensitive signal are separated from high level excite signals by locating sensitive signals on the first board and excite signals on the second board.
摘要翻译：紧凑型分解器预放大组件具有第一和第二印刷电路板。这些单板包括一个具有N / N-1解算器和分解器到数字转换器和三个信号路径的接口。第一和第二电路板被包含在被配置为安装在机器人接头上的单个封装中，同时提供高放大和噪声抑制。低电平敏感信号通过将敏感信号定位在第一板上并在第二板上激发信号与高电平激发信号分离。

9. 发明申请

US20160226508A1 Semiconductor Device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20160226508A1
公开(公告)日：2016-08-04
申请号：US14991978
申请日：2016-01-10
申请人： Renesas Electronics Corporation
发明人： Kazuaki KUROOKA , Yoshihiro FUNATO
IPC分类号： H03M1/48 , H03M1/64
CPC分类号： H03M1/485 , H03M1/0872 , H03M1/645
摘要： In a semiconductor device, a sine wave signal is input to a first input part and a cosine wave signal is input to a second input part. A multiplexer alternately selects one of the sine wave signal and the cosine wave signal. An analog to digital converter converts the output signal of the multiplexer into a digital value. A switching circuit is coupled between at least one of the first and second input parts and the multiplexer. The switching circuit is configured to be able to invert the input sine wave signal or the input cosine wave signal, in order to reduce the angle detection error due to the non-linearity error of the A/D converter.
摘要翻译：在半导体装置中，将正弦波信号输入到第一输入部，将余弦波信号输入到第二输入部。多路复用器交替地选择正弦波信号和余弦波信号之一。模数转换器将多路复用器的输出信号转换为数字值。开关电路耦合在第一和第二输入部分中的至少一个和多路复用器之间。开关电路被配置为能够反转输入正弦波信号或输入余弦波信号，以便减小由于A / D转换器的非线性误差引起的角度检测误差。

10. 发明授权

US08872682B2 Analog-to-digital conversion loop for PS15 and WSS systems 有权
标题翻译：用于PS15和WSS系统的模数转换回路
公开(公告)号：US08872682B2
公开(公告)日：2014-10-28
申请号：US13926455
申请日：2013-06-25
申请人： STMicroelectronics S.r.l
发明人： Vanni Poletto , Carlo Antonini , Salvatore Cannavacciuolo
IPC分类号： H03M1/00 , H03M1/12 , H03M3/04 , H03M1/48
CPC分类号： H03M1/12 , H03M1/1235 , H03M1/48 , H03M3/04
摘要： An analog-to-digital conversion loop adapted to generate a digital output signal corresponding to a low-pass filtered replica of an analog input signal, including an analog adder configured to receive the input analog signal and an analog feedback signal, adapted to generate an analog error signal corresponding to the difference between the analog input signal and the analog feedback signal; an analog-to-digital converter having a nonlinear input-output conversion characteristic defining a larger quantization step the more the input to be converted differs from a null value, configured to receive the analog error signal and to generate a corresponding digital error signal a digital integrator configured to receive the digital error signal, configured to generate the digital output signal corresponding to the time integration of the digital error signal; a digital-to-analog converter, configured to receive the digital output signal and to generate the analog feedback signal as analog replica of the digital output signal.
摘要翻译：一种适于产生对应于模拟输入信号的低通滤波复制品的数字输出信号的模拟 - 数字转换回路，包括配置成接收输入模拟信号的模拟加法器和模拟反馈信号，该模拟加法器适于产生模拟误差信号对应于模拟输入信号和模拟反馈信号之间的差异; 具有定义较大量化步长的非线性输入 - 输出转换特性的模数转换器，被转换的输入越多与空值不同，被配置为接收模拟误差信号并产生相应的数字误差信号，数字积分器，被配置为接收数字误差信号，被配置为产生对应于数字误差信号的时间积分的数字输出信号; 数模转换器，配置成接收数字输出信号并产生模拟反馈信号作为数字输出信号的模拟副本。

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