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1. 发明申请

US20160336927A1 LOW-RIPPLE LATCH CIRCUIT FOR REDUCING SHORT-CIRCUIT CURRENT EFFECT 有权
标题翻译：用于减少短路电流效应的低纹波锁存电路
公开(公告)号：US20160336927A1
公开(公告)日：2016-11-17
申请号：US15044114
申请日：2016-02-16
申请人： MEDIATEK INC.
发明人： Chen-Yen Ho , Yu-Hsin Lin
IPC分类号： H03K3/356 , H03M1/66
CPC分类号： H03K3/356113 , H03K3/356121 , H03K3/356191 , H03M1/066 , H03M1/0872 , H03M1/66 , H03M3/464
摘要： A latch circuit includes an input stage, an amplifying stage and a clock gating circuit. The input stage is arranged for receiving at least a clock signal and a data control signal. The amplifying stage is coupled to the input stage and supplied by a supply voltage and a ground voltage, and is arranged for retaining a data value and outputting the data value according to the clock signal and the data control signal. The clock gating circuit is coupled to the amplifying stage, and is arranged for avoiding a short-circuit current between the supply voltage and the ground voltage.
摘要翻译：锁存电路包括输入级，放大级和时钟门控电路。输入级被布置成用于接收至少一个时钟信号和数据控制信号。放大级与输入级耦合，由供电电压和接地电压提供，并被配置为保持数据值并根据时钟信号和数据控制信号输出数据值。时钟门控电路耦合到放大级，并且被布置为避免电源电压和接地电压之间的短路电流。

2. 发明申请

US20160226508A1 Semiconductor Device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20160226508A1
公开(公告)日：2016-08-04
申请号：US14991978
申请日：2016-01-10
申请人： Renesas Electronics Corporation
发明人： Kazuaki KUROOKA , Yoshihiro FUNATO
IPC分类号： H03M1/48 , H03M1/64
CPC分类号： H03M1/485 , H03M1/0872 , H03M1/645
摘要： In a semiconductor device, a sine wave signal is input to a first input part and a cosine wave signal is input to a second input part. A multiplexer alternately selects one of the sine wave signal and the cosine wave signal. An analog to digital converter converts the output signal of the multiplexer into a digital value. A switching circuit is coupled between at least one of the first and second input parts and the multiplexer. The switching circuit is configured to be able to invert the input sine wave signal or the input cosine wave signal, in order to reduce the angle detection error due to the non-linearity error of the A/D converter.
摘要翻译：在半导体装置中，将正弦波信号输入到第一输入部，将余弦波信号输入到第二输入部。多路复用器交替地选择正弦波信号和余弦波信号之一。模数转换器将多路复用器的输出信号转换为数字值。开关电路耦合在第一和第二输入部分中的至少一个和多路复用器之间。开关电路被配置为能够反转输入正弦波信号或输入余弦波信号，以便减小由于A / D转换器的非线性误差引起的角度检测误差。

3. 发明授权

US09350377B1 Digital-to-analog converter with local interleaving and resampling 有权
标题翻译：具有局部交织和重采样的数模转换器
公开(公告)号：US09350377B1
公开(公告)日：2016-05-24
申请号：US14827598
申请日：2015-08-17
申请人： Rohde & Schwarz GmbH & Co. KG
发明人： Radu Fetche , Faye Jung , Mark Lehne
IPC分类号： H03M1/66 , H03M1/76 , H03M1/70
CPC分类号： H03M1/0624 , H03M1/0863 , H03M1/0872 , H03M1/1215 , H03M1/742
摘要： The invention relates to a digital to analog converter and a method for a digital to analog conversion, wherein the digital to analog converter comprises at least one analog output cell configured to selectively generate a partial analog signal in response to a partial digital input signal. The analog output cell comprises an analog output switching unit that comprises a current source connected in series to a first node of a retiming switch and a first switch element as well as a second switching element, both connected with respect to first nodes in parallel to a second node of the retiming switch and a switching logic configured to regulate the transmission of said partial analog signal to an analog cell output.
摘要翻译：本发明涉及数模转换器和数模转换方法，其中数模转换器包括至少一个模拟输出单元，配置成响应于部分数字输入信号选择性地产生部分模拟信号。模拟输出单元包括模拟输出切换单元，其包括串联连接到重定时开关的第一节点的电流源和第一开关元件以及第二开关元件，它们相对于第一节点并联连接到第一节点重新定时开关的第二节点和被配置为调节所述部分模拟信号到模拟单元输出的传输的开关逻辑。

4. 发明申请

US20120062402A1 MULTIPLEXED AMPLIFIER WITH REDUCED GLITCHING 有权
标题翻译：多功能放大器，具有降低玻璃化
公开(公告)号：US20120062402A1
公开(公告)日：2012-03-15
申请号：US12880311
申请日：2010-09-13
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H03M1/00
CPC分类号： H03M1/0872 , H03M1/1215 , H03M1/1225 , H03M1/164 , H03M1/44
摘要： In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths.
摘要翻译：在使用以小于50％工作周期工作的放大器的许多应用中，减少数量放大器以降低功耗将是有利的。这里，提供了一种放大器，其被时分复用以容纳多个数据路径。此外，在该放大器的输出端子处提供复位电路或复位机构，以短暂地输出端子短路，以防止可能由数据路径之间切换引起的毛刺。

5. 发明授权

US07598894B2 Source driver and digital-to-analog converter thereof 有权
标题翻译：源极驱动器及其数模转换器
公开(公告)号：US07598894B2
公开(公告)日：2009-10-06
申请号：US11875283
申请日：2007-10-19
申请人： Yu-Jui Chang
发明人： Yu-Jui Chang
IPC分类号： H03M1/66
CPC分类号： H03M1/0872 , G09G3/20 , G09G2310/027 , G09G2320/0276 , H03M1/76
摘要： A source driver and a digital-to-analog converter (DAC) thereof are provided. The DAC converts an input data into an analog voltage. The DAC includes a reference voltage generation unit, a switch unit, and a selection unit. The reference voltage generation unit provides a plurality of voltage levels. The switch unit is coupled to the reference voltage generation unit and determines whether to output the voltage levels, wherein the switch unit is turned off during a data conversion period of the input data. The selection unit is coupled to the reference voltage generation unit via the switch unit, and the selection unit selects one of the voltage levels output by the switch unit according to the input data, wherein the selected voltage level is served as the analog voltage output by the DAC.
摘要翻译：提供了源极驱动器及其数模转换器（DAC）。 DAC将输入数据转换为模拟电压。 DAC包括参考电压产生单元，开关单元和选择单元。参考电压产生单元提供多个电压电平。开关单元耦合到参考电压产生单元，并且确定是否输出电压电平，其中在输入数据的数据转换周期期间开关单元截止。选择单元经由开关单元耦合到参考电压产生单元，并且选择单元根据输入数据选择由开关单元输出的电压电平之一，其中所选择的电压电平被用作由 DAC。

6. 发明授权

US07170435B2 Method for operating an analog to digital converter 失效
标题翻译：用于操作模数转换器的方法
公开(公告)号：US07170435B2
公开(公告)日：2007-01-30
申请号：US10810053
申请日：2004-03-26
申请人： Klaas Bult , Chi-Hung Lin
发明人： Klaas Bult , Chi-Hung Lin
IPC分类号： H03M1/66
CPC分类号： H03M1/0624 , H03M1/0682 , H03M1/0872 , H03M1/685 , H03M1/747
摘要： Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.
摘要翻译：二进制指示被转换为模拟表示，在连续的二进制指示之间的转换和每个二进制指示期间的周期中显着地减少振铃。二进制指示以行和列矩阵布置以提供温度计代码。转换器的每个级包括一个解码器和锁存器，所述解码器和锁存器布置成使得解码器输入在锁存器被时钟脉冲设置之前稳定。这些阶段在互补CMOS中实现。互补晶体管是偏置的，因此该对的一个晶体管被驱动到轨道，而另一个晶体管则浮动。虚拟CMOS晶体管用于平衡解码器路径中的晶体管数量。

7. 发明申请

US20040164887A1 SWITCHING DAC PULSE ENCODING CIRCUIT 有权
标题翻译：切换DAC脉冲编码电路
公开(公告)号：US20040164887A1
公开(公告)日：2004-08-26
申请号：US10374250
申请日：2003-02-25
发明人： William M. Skones , Steve R. Nelson
IPC分类号： H03M001/66
CPC分类号： H03M3/502 , H03M1/0624 , H03M1/0872 , H03M1/742
摘要： A DAC including a first switch and a second switch. The first switch receives a digital signal to be converted, and the second switch receives the digital signal delayed by one-half of a clock signal. A third switch receives a current signal from a current source and the clock signal. The third switch alternately switches the current signal to the first and second switches so that when the clock signal is positive, the current signal is applied to the first switch and when the clock signal is zero, the current signal is applied to the second switch. The first switch will output the current signal during the first half of the clock cycle to a first output or a second output, and the second switch will output the current signal during the second half of the clock cycle to the first output or the second output.
摘要翻译：包括第一开关和第二开关的DAC。第一开关接收要转换的数字信号，并且第二开关接收延迟了时钟信号的二分之一的数字信号。第三开关从电流源和时钟信号接收电流信号。第三开关交替地将电流信号切换到第一和第二开关，使得当时钟信号为正时，电流信号被施加到第一开关，并且当时钟信号为零时，电流信号被施加到第二开关。第一个开关将在时钟周期的前一半期间将当前信号输出到第一个输出或第二个输出，第二个开关将在时钟周期的后半段输出当前信号到第一个输出或第二个输出。

8. 发明申请

US20040130472A1 Pulse width modulation digital amplifier 失效
标题翻译：脉宽调制数字放大器
公开(公告)号：US20040130472A1
公开(公告)日：2004-07-08
申请号：US10740754
申请日：2003-12-22
申请人： Renesas Technology Corp.
发明人： Masako Arizumi , Hiroyuki Harada
IPC分类号： H03M001/82
CPC分类号： H03F3/217 , H03M1/0872 , H03M1/822 , H03M3/376 , H03M3/506
摘要： In a digital amplifier, a time controller generates first and second selection signals for outputting any one of music data, a center output, and a lowest output to a P output and an N output based on a power ON/OFF signal and a start/stop signal, and also generates a third selection signal for determining whether a signal having the same phase as that of the P output is output to the N output or a signal obtained by inverting the P output is output to the N output. A data selection circuit determines data to be output to the P output and the N output based on the first and second selection signals. An output data register circuit converts parallel data determined by the data selection circuit into serial data to output the serial data into the P output. An output selection circuit determines the N output based on the third selection signal.
摘要翻译：在数字放大器中，时间控制器产生用于将音频数据，中心输出和最低输出中的任何一个输出到P输出和N输出的第一和第二选择信号，其基于电源ON / OFF信号和开始/ 并且还产生用于确定与P输出具有相同相位的信号是否被输出到N输出的第三选择信号或者通过将P输出反相获得的信号被输出到N输出。数据选择电路基于第一和第二选择信号确定要输出到P输出和N输出的数据。输出数据寄存器电路将由数据选择电路确定的并行数据转换成串行数据，将串行数据输出到P输出。输出选择电路根据第三选择信号确定N输出。

9. 发明申请

US20030085829A1 Digital to analog converter with reduced ringing 有权
公开(公告)号：US20030085829A1
公开(公告)日：2003-05-08
申请号：US10320016
申请日：2002-12-16
申请人： Broadcom Corporation
发明人： Klaas Bult , Chi-Hung Lin
IPC分类号： H03M001/66
CPC分类号： H03M1/0624 , H03M1/0682 , H03M1/0872 , H03M1/685 , H03M1/747
摘要： Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

10. 发明授权

US06549196B1 D/A conversion circuit and liquid crystal display device 失效
标题翻译： D / A转换电路和液晶显示装置
公开(公告)号：US06549196B1
公开(公告)日：2003-04-15
申请号：US09401847
申请日：1999-09-22
申请人： Takashi Taguchi , Takeshi Shima , Tetsuro Itakura
发明人： Takashi Taguchi , Takeshi Shima , Tetsuro Itakura
IPC分类号： B09G500
CPC分类号： H03M1/0872 , G09G3/3688 , G09G2310/027 , H03M1/765
摘要： A D/A conversion circuit which can perform D/A conversion at high speed and with high precision is disclosed. The D/A conversion circuit comprises an analog reference power supply, an output buffer, a multiplexer, a pre-buffer, and a current changeover switch. The pre-buffer operates with a power supply voltage different from that of the analog reference power supply, and outputs a voltage substantially equal to an output voltage of the analog reference power supply. For a predetermined period after logic of digital data changes, the output voltage of the pre-buffer is supplied to the output buffer, and an input parasitic capacitor of the output buffer is charged/discharged. After the predetermined period elapses, the output voltage of the analog reference power supply is supplied to the output buffer. Therefore, a charging/discharging current of the input parasitic capacitor does not flow through the analog reference power supply, and fluctuation of the output voltage of the analog reference power supply can be suppressed.
摘要翻译：公开了一种可以高速，高精度地执行D / A转换的D / A转换电路。 D / A转换电路包括模拟参考电源，输出缓冲器，多路复用器，预缓冲器和电流切换开关。预缓冲器以与模拟基准电源不同的电源电压工作，并输出基本上等于模拟基准电源的输出电压的电压。在数字数据的逻辑变化之后的预定时间内，预缓冲器的输出电压被提供给输出缓冲器，并且输出缓冲器的输入寄生电容器被充电/放电。经过预定时间后，模拟基准电源的输出电压被提供给输出缓冲器。因此，输入的寄生电容器的充电/放电电流不会流过模拟基准电源，并且可以抑制模拟基准电源的输出电压的波动。

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