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1. 发明授权

US11243078B2 FTR loop of a gyro apparatus 有权
公开(公告)号：US11243078B2
公开(公告)日：2022-02-08
申请号：US16361680
申请日：2019-03-22
申请人： Panasonic Intellectual Property Management Co., Ltd.
发明人： Chihchuan Che , Yaesuk Jeong
IPC分类号： G01C19/5776 , H03M1/06 , H03M1/08 , H03M1/18 , H03M1/50 , H03M1/82
摘要： A signal processing circuit for a gyroscope apparatus is disclosed. The signal processing circuit includes a first electrode and a second electrode pairing with the first electrode. The signal processing circuit, being a negative feedback loop circuit, is configured to be connected with the first electrode and the second electrode and comprises a demodulator configured to convert a current from the first electrode into a voltage and demodulate the converted voltage to output a demodulated signal, an analog-to-digital converter configured to convert the demodulated signal from the demodulator into a digital signal, a proportional-integral-derivative controller that is connected to the analog-to-digital converter, a digital-to-analog converter configured to convert an output signal from the proportional-integral-derivative controller to an analog signal, and a modulator configured to be electrically connected with the second electrode and to be electrically connected with the digital-to-analog converter.

2. 发明授权

US11184018B1 Mismatch and timing correction technique for mixing-mode digital-to-analog converter (DAC) 有权
公开(公告)号：US11184018B1
公开(公告)日：2021-11-23
申请号：US17087234
申请日：2020-11-02
申请人： QUALCOMM Incorporated
发明人： Xilin Liu , Parisa Mahmoudidaryan , Shahin Mehdizad Taleie , Negar Rashidi , Dongwon Seo
IPC分类号： H03M1/18 , H03M1/82 , H03M1/06 , H03M1/10 , H03K5/156 , H03K5/05 , H03M1/80 , H03K5/00
摘要： Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. For example, certain aspects provide an apparatus for digital-to-analog conversion. The apparatus generally includes a mixing-mode digital-to-analog converter (DAC), a duty cycle adjustment circuit having an input coupled to an input clock node and having an output coupled to a clock input of the mixing-mode DAC, and a current comparison circuit having inputs coupled to outputs of the mixing-mode DAC and having an output coupled to a control input of the duty cycle adjustment circuit.

3. 发明申请

US20210200256A1 MULTI-PHASE CLOCK SIGNAL PHASE DIFFERENCE DETECTION AND CALCULATION CIRCUIT AND METHOD AND DIGITAL PHASE MODULATION SYSTEM 有权
公开(公告)号：US20210200256A1
公开(公告)日：2021-07-01
申请号：US17134201
申请日：2020-12-25
申请人： Montage LZ Technologies (Xiamen) Co., Ltd.
发明人： Mingfu SHI , Shunfang WU , Shen FENG , Jun XU , Xinwu CAI
IPC分类号： G06F1/08 , H03M1/82 , G01R25/00 , G06F1/14
摘要： The present disclosure provides a multi-phase clock signal phase difference detection and calculation circuit and method, and a digital phase modulation system. The detection and calculation circuit includes an auxiliary digital-to-time conversion circuit, a main digital-to-time conversion circuit, a phase detector, and a state machine. The auxiliary digital-to-time conversion circuit selects a first phase clock signal and outputs an auxiliary clock signal, adjusts the phase of the auxiliary clock signal; the phase detector detects the phases of the auxiliary clock signal and a target clock signal output by the main digital-to-time conversion circuit; the state machine adjusts the phase of the auxiliary clock signal, and adjusts the phase of the target clock signal. When the phase difference between the two signals is zero, the amount of phase adjustment by the main digital-to-time conversion circuit is the phase difference between the first phase clock signal and the second phase clock signal.

4. 发明申请

US20200328752A1 Time To Digital Converter And A/D Conversion Circuit 审中-公开
公开(公告)号：US20200328752A1
公开(公告)日：2020-10-15
申请号：US16847712
申请日：2020-04-14
申请人： Seiko Epson Corporation
发明人： Masayoshi TODOROKIHARA
IPC分类号： H03M1/12 , G04F10/00 , H03M1/82
摘要： There is provided a time to digital converter to which a reference signal and a trigger signal are input, the time to digital converter outputting a time digital value corresponding to a time event of the trigger signal with respect to the reference signal, the time to digital converter including a state transition section configured to output state information indicating an internal state and start, based on the trigger signal, state transition in which the internal state transitions, a transition-state acquiring section configured to acquire, in synchronization with the reference signal, the state information from the state transition section and hold the state information, and an arithmetic operation section configured to calculate, based on the state information acquired by the transition-state acquiring section, the time digital value corresponding to a number of times of transition of the internal state. A time from when the internal state transitions from a first internal state to a second internal state until when the internal state reverts to the first internal state is longer than a cycle in which the state information held by the transition-state acquiring section is updated.

5. 发明授权

US10666241B2 Variable delay circuit 有权
公开(公告)号：US10666241B2
公开(公告)日：2020-05-26
申请号：US16194150
申请日：2018-11-16
申请人： ROHM CO., LTD. , Stichting IMEC Nederland
发明人： Takashi Kuramochi , Yao Hong Liu
IPC分类号： H03K5/131 , H03K5/153 , H03L7/085 , H03L7/197 , H03M1/82 , H03K5/00
摘要： A variable delay circuit, which includes a digital-to-time converter (DTC) circuit and a controller, is disclosed. The DTC circuit includes a plurality of capacitors and a plurality of MOS switches that are turned on and off according to a control code. The DTC circuit receives an input pulse, applies a delay corresponding to the control code to the edge to be delayed, and outputs a delay pulse. The controller supplies a valid code indicating a delay amount as a control code during a period beginning from a predetermined time TCONST before the edge (positive edge) to be delayed of an input pulse REF up to the edge to be delayed. Further, the controller supplies, as the control code, a dummy code for turning on all of the plurality of MOS switches inside the DTC circuit immediately before the period.

6. 发明申请

US20200144996A1 PULSE-WIDTH MODULATION 审中-公开
公开(公告)号：US20200144996A1
公开(公告)日：2020-05-07
申请号：US16735297
申请日：2020-01-06
申请人： Cirrus Logic International Semiconductor Ltd.
发明人： Toru IDO
IPC分类号： H03K7/08 , H03F3/217 , H03M1/82
摘要： This application relates to digital PWM modulation. A PWM modulator (400, 1100) has a PWM generator (402) configured to receive pulse width data (PWidth) and to output a PWM signal (SPWM) comprising a plurality of repeating PWM cycle periods, in which the duration of any pulse of the PWM signal in each PWM cycle period is based on the pulse width data. The PWM generator is configured to synchronise the PWM cycle periods, and the start and end of any PWM pulse, to a received first clock signal. The PWM generator is operable to generate pulses that have a positional error from a centred position within the PWM cycle period and a pulse position controller (403) is configured to control the position of a pulse in a PWM cycle period so as to at least partly compensate for the positional error of one or more preceding pulses.

7. 发明授权

US10381926B2 Digitally compensated hysteretic power supply with enhanced resolution 有权
公开(公告)号：US10381926B2
公开(公告)日：2019-08-13
申请号：US14864838
申请日：2015-09-24
申请人： Peng Xiao , Markus Ziegler
发明人： Peng Xiao , Markus Ziegler
IPC分类号： H02M3/157 , H02M7/5395 , H03M1/68 , H02M3/156 , H03M1/82 , H05B33/08 , H02M1/00
摘要： A digitally compensated hysteretic power supply with enhanced resolution is provided. Such a power supply includes a comparator that is used to compare a load current sense signal with an internal signal generated from a digital-to-analog converter (DAC). A compensation circuit at a DAC input operates to improve current accuracy beyond the given DAC resolution. The current sense signal is converted to its digital equivalent, which is fed to a proportional-integral (PI) compensation loop, which in turn generates a relatively precise high resolution DAC input value. The DAC uses the higher part of the DAC value. The lower part of the DAC value is treated as a duty cycle number, and the DAC output is toggled between two levels at this duty cycle. This toggling generates a current output signal having a value that is the average of the two toggled values.

8. 发明授权

US10243580B1 Digital to analog converter with iterative stepping to each output value 有权
公开(公告)号：US10243580B1
公开(公告)日：2019-03-26
申请号：US15984623
申请日：2018-05-21
申请人： Southwest Research Institute
发明人： Mark A. Johnson
IPC分类号： H03M1/82 , H03M1/46
摘要： A digital to analog converter (DAC) that provides an output that is iteratively stepped as the DAC increments or decrements from its digital input to analog output. The DAC has configurable registers to store a timer count value, an iteration value, and the input value. A state machine compares the iteration value to current DAC values, and adds or subtracts the iteration value until the final output is reached.

9. 发明申请

US20180269895A1 DIGITAL-TO-TIME CONVERTER AND OPERATING METHOD THEREOF 审中-公开
公开(公告)号：US20180269895A1
公开(公告)日：2018-09-20
申请号：US15869854
申请日：2018-01-12
申请人： Samsung Electronics Co., Ltd.
发明人： Nam-seog KIM
IPC分类号： H03M1/82 , H03M1/78 , H03L7/097 , G04F10/00 , H03K5/131 , H03F3/217 , H03K5/135
CPC分类号： H03M1/825 , G04F10/005 , H03F3/2175 , H03K5/131 , H03K5/135 , H03L7/097 , H03M1/68 , H03M1/785
摘要： A digital-to-time converter includes: a digital-to-analog converter configured to generate a precharge voltage corresponding to a value of a digital code; a ramp generator configured to precharge a capacitor connected to a first node based on the precharge voltage, and to charge or discharge the capacitor based on a reference current provided from a current source in response to a transition of an input clock signal to generate a ramp voltage in the first node; and a comparator configured to generate an output clock signal based on the ramp voltage, wherein the ramp generator includes: a first switching circuit configured to provide a first current path between a second node connected to the current source and the first node; and a second switching circuit configured to provide a second current path from a power supply voltage source to the second node.

10. 发明授权

US09748968B1 Extreme index finder and finding method thereof 有权
公开(公告)号：US09748968B1
公开(公告)日：2017-08-29
申请号：US15415674
申请日：2017-01-25
申请人： National Tsing Hua University
发明人： Mao-Ruei Li , Chia-Hsiang Yang , Yeong-Luh Ueng
IPC分类号： H03M1/82
CPC分类号： H03M1/82 , H03M1/123
摘要： An extreme index finder and a digital value finding method are provided. The extreme index finder includes a plurality of digital-to-time converters (DTCs) and a first arbiter apparatus. The DTCs respectively receive a plurality of input signals and perform a digital-to-time converting operation on each of the input signals to respectively generate a plurality of time-domain signals. The first arbiter apparatus finds a position of a extreme value in the time-domain signals according to transition speeds of the time-domain signals and compares transition speed of the extreme value with each of the time-domain signals to find an extreme input signal corresponding to the extreme value in the input signals.

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