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1. 发明申请

US20190097584A1 ENVELOPE-SHAPED BIAS FOR POWER AMPLIFIER 审中-公开
公开(公告)号：US20190097584A1
公开(公告)日：2019-03-28
申请号：US16138647
申请日：2018-09-21
申请人： QUALCOMM Incorporated
发明人： Chenliang Du
IPC分类号： H03F1/02 , H03F3/217 , H03F3/193
CPC分类号： H03F1/0222 , H03F3/191 , H03F3/193 , H03F3/2175 , H03F3/245 , H03F2200/102 , H03F2200/411 , H03F2200/451
摘要： This disclosure provides systems, methods and apparatuses for characterizing and operating a power amplifier. Before being placed into operation, output phase and output gain characteristics of the power amplifier may be determined over various operating conditions including varying two independent control signals and a supply voltage. The output phase and output gain characteristics may be stored for later retrieval. The power amplifier may be operated by determining a control signal profile for the two independent control signals based on operating conditions and radio-frequency (RF) envelope information associated with an input signal received by the power amplifier. The independent control signals may be generated in accordance with the control signal profile.

2. 发明申请

US20190007011A1 AMPLIFIER CIRCUIT 审中-公开
公开(公告)号：US20190007011A1
公开(公告)日：2019-01-03
申请号：US16001127
申请日：2018-06-06
申请人： NXP B.V.
发明人： Marco Berkhout
IPC分类号： H03F3/217 , H03K7/08 , H03M3/00
CPC分类号： H03F3/2175 , H03F3/2171 , H03F3/2173 , H03F2200/331 , H03K7/08 , H03M3/432 , H03M3/456 , H03M3/50 , H03M3/506
摘要： An amplifier circuit comprising: a delta-PWM-modulator, a three-level-DAC, a loop-integrator, and a comparator. The delta-PWM-modulator receives a digital-input-signal; and processes the digital-input-signal and a modulator-triangular-signal to generate a delta-pulse-width-modulation-signal. The delta-pulse-width-modulation-signal is representative of the difference between a square-wave-carrier-signal and a digital-pulse-width-modulation of the digital-input-signal. The three-level-DAC receives the delta-pulse-width-modulation-signal from the delta-PWM-modulator and provides a three-level-analogue-signal. The loop-integrator comprises: a virtual-ground-node-terminal configured to receive: (i) the three-level-analogue-signal from the three-level DAC; and (ii) a feedback-signal from an output stage of the amplifier circuit via a feedback loop; and an integrator-output-terminal configured to provide a loop-integrator-output-signal. The comparator comprises a comparator-input-terminal configured to receive the loop-integrator-output-signal; a comparator-reference-terminal configured to receive a triangular-reference-signal that corresponds to the integral of the square-wave-carrier-signal; and a comparator-output-terminal configured to provide a drive-signal suitable for driving an output-stage of the amplifier circuit.

3. 发明授权

US10044383B2 Sinewave generation from multi-phase signals 有权
公开(公告)号：US10044383B2
公开(公告)日：2018-08-07
申请号：US15395033
申请日：2016-12-30
申请人： Silicon Laboratories Inc.
发明人： Aaron J. Caffee , Brian G. Drost , Alessandro Piovaccari , Aslamali A. Rafi
IPC分类号： H04B1/04 , H04L27/36 , H04B3/06 , H04L7/033 , H03F1/32 , H03F1/02 , H03F3/19 , H03F3/21 , H03L7/08
CPC分类号： H04B1/0475 , H03F1/0294 , H03F1/32 , H03F3/19 , H03F3/211 , H03F3/2175 , H03F3/245 , H03F2200/451 , H03F2200/537 , H03F2200/541 , H03L7/08 , H03L2207/50 , H04B3/06 , H04B2001/045 , H04L27/364 , H04L2027/0018 , H04L2027/0055
摘要： A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.

4. 发明申请

US20180159490A1 CLASS D AMPLIFIER CIRCUIT 审中-公开
公开(公告)号：US20180159490A1
公开(公告)日：2018-06-07
申请号：US15886103
申请日：2018-02-01
申请人： Cirrus Logic International Semiconductor Ltd.
发明人： John Paul LESSO , Toru IDO
IPC分类号： H03G3/30 , H03F1/26 , H03F1/32 , H03F3/187 , H03F3/217 , H03F1/34 , H03G7/00
CPC分类号： H03G3/3089 , H03F1/26 , H03F1/32 , H03F1/34 , H03F3/187 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/2175 , H03F2200/102 , H03F2200/339 , H03F2200/432 , H03G7/002 , H03G7/007
摘要： This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ϵ) from the output signal and the input signal. In various embodiments the extent to which the error signal (ϵ) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205).

5. 发明授权

US09991904B2 Digital modulation device, and digital modulation method 有权
公开(公告)号：US09991904B2
公开(公告)日：2018-06-05
申请号：US15513266
申请日：2015-09-17
申请人： NEC Corporation
发明人： Shinichi Hori
IPC分类号： H03M3/00 , H03F3/217 , H03M9/00 , H04L27/36
CPC分类号： H03M3/39 , H03F3/217 , H03F3/2175 , H03F3/24 , H03F2200/171 , H03F2200/331 , H03M3/456 , H03M3/47 , H03M9/00 , H04L27/36
摘要： A digital modulation device is provided. The digital modulation device includes an input unit; N delta-sigma modulation units; and an output unit. N is an integer greater than or equal to 2, the input unit is configured to: input initial values which differ from each other to the N delta-sigma modulation units; and then, input a same first signal into the N delta-sigma modulation units, each of the N delta-sigma modulation units is configured to: output a second signal by performing delta-sigma modulation processing on the first signal for each first clock cycle, and the output unit is configured to: sequentially output each second signal for each one Nth of the first clock cycle.

6. 发明申请

US20180145700A1 High Efficiency Power Amplifier Architectures for RF Applications 审中-公开
公开(公告)号：US20180145700A1
公开(公告)日：2018-05-24
申请号：US15819475
申请日：2017-11-21
申请人： MY Tech, LLC
发明人： Tommy Yu , Avanindra Madisetti
IPC分类号： H03M3/00 , H03F3/217 , H03F3/19
CPC分类号： H03M3/39 , H03F1/0227 , H03F3/19 , H03F3/2171 , H03F3/2175 , H03F3/245 , H03F2200/102 , H03F2200/171 , H03F2200/451 , H03M7/3004
摘要： A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.

7. 发明授权

US09949031B2 Class-D amplifier with pulse density modulation output feedback for higher performance acoustic echo canceller 有权
公开(公告)号：US09949031B2
公开(公告)日：2018-04-17
申请号：US13860477
申请日：2013-04-10
申请人： SYNAPTICS INCORPORATED
发明人： Mouna Elkhatib , Trausti Thormundsson , Jonathan Chien , Yair Kerner
IPC分类号： H04R3/12 , H04R3/02 , H03F3/217
CPC分类号： H04R3/12 , H03F3/2175 , H04R3/02 , H04R2499/15
摘要： A system for processing audio data comprising an amplifier configured to receive an audio signal and to perform nonlinear processing on the audio signal. An encoder coupled to the amplifier, the encoder configured to receive the nonlinearly processed audio signal and to encode the nonlinearly processed audio signal into a data transmission format. A transmitter configured to receive and transmit the encoded nonlinearly processed audio signal. A receiver configured to receive the transmitted encoded nonlinearly processed audio signal and to decode the encoded nonlinearly processed audio signal. A digital voice processor configured to receive the nonlinearly processed audio signal and to use the nonlinearly processed audio signal for echo estimation and to subsequently subtract the estimated echo signal from a microphone signal.

8. 发明授权

US09912238B1 Determination of inductor current during reverse current in a boost converter 有权
公开(公告)号：US09912238B1
公开(公告)日：2018-03-06
申请号：US14182939
申请日：2014-02-18
申请人： Cirrus Logic, Inc.
发明人： Ullas Pazhayaveetil , Jeffrey May , Gautham D. Kamath , John Christopher Tucker , Christian Larsen
IPC分类号： G05F1/00 , H02M3/158 , H02M3/156
CPC分类号： H02M3/158 , G01R21/06 , G01R27/2611 , G06F1/3203 , H02M3/156 , H03F3/187 , H03F3/2175 , H03G3/004
摘要： During operation of a boost converter conditions may exist that result in a reverse current through the boost converter, such as when a load drop from the boost converter occurs. During the reverse current period, inductance value determinations made during a forward current period may be used to estimate a magnitude of the reverse current and this estimate used by a controller to control the boost converter and return the boost converter to normal operation. The controller may control the boost converter by changing a ratio of charging and discharging time for an inductor of the boost converter, decreasing a bandwidth of the boost converter, and/or increasing a resistance of the boost converter.

9. 发明申请

US20180041176A1 System and Methods of RF Power Transmission, Modulation, and Amplification, Including Control Functions to Transition an Output of a MISO Device 审中-公开
公开(公告)号：US20180041176A1
公开(公告)日：2018-02-08
申请号：US15470738
申请日：2017-03-27
申请人： ParkerVision, Inc.
发明人： Gregory S. Rawlins , David F. Sorrells
IPC分类号： H03F3/195 , H03F3/213 , H03F1/02 , H03F3/217 , H03F3/21
CPC分类号： H03F3/195 , H03F1/0294 , H03F3/211 , H03F3/213 , H03F3/2175 , H03F2200/451 , H03F2203/21106
摘要： Embodiments of the present invention include a method and system for control of a multiple-input-single output (MISO) device. For example, the method includes partitioning a waveform constellation space into a plurality of regions, where each region of the plurality of regions is associated with one or more control functions of the MISO device. The method also includes transitioning the MISO device between a plurality of classes of operation based on the one or more control functions.

10. 发明授权

US09716469B2 Amplification systems and methods with one or more channels 有权
公开(公告)号：US09716469B2
公开(公告)日：2017-07-25
申请号：US14584907
申请日：2014-12-29
申请人： ON-BRIGHT ELECTRONICS (SHANGHAI) CO., LTD.
发明人： Tingzhi Yuan , Yaozhang Chen , Lieyi Fang
IPC分类号： H03F3/38 , H03L7/00 , H03F1/02 , H03F3/217 , H03F3/185 , H03F3/45 , H03F3/68
CPC分类号： H03F1/0205 , H03F3/185 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/2175 , H03F3/45071 , H03F3/45475 , H03F3/68 , H03F2200/03 , H03F2200/171 , H03F2200/351 , H03F2200/78 , H03F2203/21106 , H03F2203/21145 , H03F2203/21157
摘要： Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes a first channel, a second channel, and a third channel. The first channel is configured to receive one or more first input signals, process information associated with the one or more first input signals and a first ramp signal, and generate one or more first output signals. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and a second ramp signal, and generate one or more second output signals. The first ramp signal corresponds to a first phase. The second ramp signal corresponds to a second phase. The first phase and the second phase are different.

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